soc/amd/stoneyridge: Revise pci_devs.h file
Now that pci_devs.h is part of soc/ and not used for multiple southbridges: * Remove devices not present in the Stoney Ridge APU * Complete the list to include additional devices besides those in the FCH. BUG=chrome-os-partner:62578372 Change-Id: I1cd2d5e41473f362bbfd28ee93788a292bc33991 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20370 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Marshall Dawson
Martin Roth
parent
9d6b8b4d68
commit
12983db91d
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@ -16,7 +16,236 @@
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#ifndef _PI_STONEYRIDGE_PCI_DEVS_H_
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#define _PI_STONEYRIDGE_PCI_DEVS_H_
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#define BUS0 0
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#include <device/pci_def.h>
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#include <rules.h>
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/* HT Configuration */
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#define HT_DEV 0x18
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#define HT_FUNC 0
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#define HT_DEVID 0x15b0
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#define HT_DEVFN PCI_DEVFN(HT_DEV, HT_FUNC)
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/* Address Maps */
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#define ADDR_DEV 0x18
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#define ADDR_FUNC 1
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#define ADDR_DEVID 0x15b1
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#define ADDR_DEVFN PCI_DEVFN(ADDR_DEV, ADDR_FUNC)
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/* DRAM Configuration */
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#define DCT_DEV 0x18
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#define DCT_FUNC 2
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#define DCT_DEVID 0x15b2
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#define DCT_DEVFN PCI_DEVFN(DCT_DEV, DCT_FUNC)
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/* Misc. Configuration */
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#define MISC_DEV 0x18
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#define MISC_FUNC 3
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#define MISC_DEVID 0x15b3
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#define MISC_DEVFN PCI_DEVFN(MISC_DEV, MISC_FUNC)
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/* PM Configuration */
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#define PM_DEV 0x18
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#define PM_FUNC 4
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#define PM_DEVID 0x15b4
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#define PM_DEVFN PCI_DEVFN(PM_DEV, PM_FUNC)
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#if !defined(__SIMPLE_DEVICE__)
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#include <device/device.h>
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#define DEV_D18F4 dev_find_slot(0, PM_DEVFN)
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#else
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#define DEV_D18F4 PCI_DEV(0, PM_DEV, PM_FUNC)
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#endif
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/* Northbridge Configuration */
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#define NB_DEV 0x18
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#define NB_FUNC 5
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#define NB_DEVID 0x15b5
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#define NB_DEVFN PCI_DEVFN(NB_DEV, NB_FUNC)
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/* GNB Root Complex */
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#define GNB_DEV 0x0
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#define GNB_FUNC 0
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#define GNB_DEVID 0x1576
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#define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC)
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/* IOMMU */
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#define IOMMU_DEV 0x0
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#define IOMMU_FUNC 2
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#define IOMMU_DEVID 0x1577
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#define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC)
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/* Internal Graphics */
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#define GFX_DEV 0x1
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#define GFX_FUNC 0
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#define GFX_DEVID 098e4 /* subject to SKU/OPN variation */
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#define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC)
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/* HD Audio 0 */
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#define HDA0_DEV 0x1
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#define HDA0_FUNC 1
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#define HDA0_DEVID 015b3
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#define HDA0_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC)
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/* Host Bridge */
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#define HOST_DEV 0x2
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#define HOST_FUNC 0
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#define HOST_DEVID 0x157b
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#define HOST_DEVFN PCI_DEVFN(HOST_DEV, HOST_FUNC)
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/* PCIe GPP Bridge 0 */
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#define PCIE0_DEV 0x2
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#define PCIE0_FUNC 1
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#define PCIE0_DEVID 0x157c
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#define PCIE0_DEVFN PCI_DEVFN(PCIE0_DEV, PCIE0_FUNC)
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/* PCIe GPP Bridge 1 */
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#define PCIE1_DEV 0x2
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#define PCIE1_FUNC 2
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#define PCIE1_DEVID 0x157c
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#define PCIE1_DEVFN PCI_DEVFN(PCIE1_DEV, PCIE1_FUNC)
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/* PCIe GPP Bridge 2 */
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#define PCIE2_DEV 0x2
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#define PCIE2_FUNC 3
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#define PCIE2_DEVID 0x157c
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#define PCIE2_DEVFN PCI_DEVFN(PCIE2_DEV, PCIE2_FUNC)
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/* PCIe GPP Bridge 3 */
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#define PCIE3_DEV 0x2
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#define PCIE3_FUNC 4
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#define PCIE3_DEVID 0x157c
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#define PCIE3_DEVFN PCI_DEVFN(PCIE3_DEV, PCIE3_FUNC)
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/* PCIe GPP Bridge 4 */
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#define PCIE4_DEV 0x2
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#define PCIE4_FUNC 5
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#define PCIE4_DEVID 0x157c
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#define PCIE4_DEVFN PCI_DEVFN(PCIE4_DEV, PCIE4_FUNC)
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/* Platform Security Processor */
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#define PSP_DEV 0x8
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#define PSP_FUNC 0
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#define PSP_DEVID 0x1578
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#define PSP_DEVFN PCI_DEVFN(PSP_DEV, PSP_FUNC)
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/* HD Audio 1 */
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#define HDA1_DEV 0x9
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#define HDA1_FUNC 2
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#define HDA1_DEVID 0x157a
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#define HDA1_DEVFN PCI_DEVFN(HDA1_DEV, HDA1_FUNC)
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/* HT Configuration */
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#define HT_DEV 0x18
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#define HT_FUNC 0
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#define HT_DEVID 0x15b0
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#define HT_DEVFN PCI_DEVFN(HT_DEV, HT_FUNC)
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/* Address Maps */
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#define ADDR_DEV 0x18
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#define ADDR_FUNC 1
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#define ADDR_DEVID 0x15b1
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#define ADDR_DEVFN PCI_DEVFN(ADDR_DEV, ADDR_FUNC)
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/* DRAM Configuration */
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#define DCT_DEV 0x18
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#define DCT_FUNC 2
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#define DCT_DEVID 0x15b2
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#define DCT_DEVFN PCI_DEVFN(DCT_DEV, DCT_FUNC)
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/* Misc. Configuration */
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#define MISC_DEV 0x18
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#define MISC_FUNC 3
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#define MISC_DEVID 0x15b3
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#define MISC_DEVFN PCI_DEVFN(MISC_DEV, MISC_FUNC)
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/* PM Configuration */
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#define PM_DEV 0x18
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#define PM_FUNC 4
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#define PM_DEVID 0x15b4
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#define PM_DEVFN PCI_DEVFN(PM_DEV, PM_FUNC)
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#if !defined(__SIMPLE_DEVICE__)
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#include <device/device.h>
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#define DEV_D18F4 dev_find_slot(0, PM_DEVFN)
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#else
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#define DEV_D18F4 PCI_DEV(0, PM_DEV, PM_FUNC)
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#endif
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/* Northbridge Configuration */
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#define NB_DEV 0x18
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#define NB_FUNC 5
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#define NB_DEVID 0x15b5
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#define NB_DEVFN PCI_DEVFN(NB_DEV, NB_FUNC)
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/* GNB Root Complex */
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#define GNB_DEV 0x0
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#define GNB_FUNC 0
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#define GNB_DEVID 0x1576
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#define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC)
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/* IOMMU */
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#define IOMMU_DEV 0x0
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#define IOMMU_FUNC 2
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#define IOMMU_DEVID 0x1577
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#define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC)
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/* Internal Graphics */
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#define GFX_DEV 0x1
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#define GFX_FUNC 0
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#define GFX_DEVID 098e4 /* subject to SKU/OPN variation */
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#define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC)
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/* HD Audio 0 */
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#define HDA0_DEV 0x1
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#define HDA0_FUNC 1
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#define HDA0_DEVID 015b3
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#define HDA0_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC)
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/* Host Bridge */
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#define HOST_DEV 0x2
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#define HOST_FUNC 0
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#define HOST_DEVID 0x157b
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#define HOST_DEVFN PCI_DEVFN(HOST_DEV, HOST_FUNC)
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/* PCIe GPP Bridge 0 */
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#define PCIE0_DEV 0x2
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#define PCIE0_FUNC 1
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#define PCIE0_DEVID 0x157c
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#define PCIE0_DEVFN PCI_DEVFN(PCIE0_DEV, PCIE0_FUNC)
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/* PCIe GPP Bridge 1 */
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#define PCIE1_DEV 0x2
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#define PCIE1_FUNC 2
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#define PCIE1_DEVID 0x157c
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#define PCIE1_DEVFN PCI_DEVFN(PCIE1_DEV, PCIE1_FUNC)
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/* PCIe GPP Bridge 2 */
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#define PCIE2_DEV 0x2
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#define PCIE2_FUNC 3
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#define PCIE2_DEVID 0x157c
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#define PCIE2_DEVFN PCI_DEVFN(PCIE2_DEV, PCIE2_FUNC)
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/* PCIe GPP Bridge 3 */
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#define PCIE3_DEV 0x2
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#define PCIE3_FUNC 4
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#define PCIE3_DEVID 0x157c
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#define PCIE3_DEVFN PCI_DEVFN(PCIE3_DEV, PCIE3_FUNC)
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/* PCIe GPP Bridge 4 */
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#define PCIE4_DEV 0x2
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#define PCIE4_FUNC 5
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#define PCIE4_DEVID 0x157c
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#define PCIE4_DEVFN PCI_DEVFN(PCIE4_DEV, PCIE4_FUNC)
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/* Platform Security Processor */
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#define PSP_DEV 0x8
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#define PSP_FUNC 0
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#define PSP_DEVID 0x1578
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#define PSP_DEVFN PCI_DEVFN(PSP_DEV, PSP_FUNC)
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/* HD Audio 1 */
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#define HDA1_DEV 0x9
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#define HDA1_FUNC 2
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#define HDA1_DEVID 0x157a
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#define HDA1_DEVFN PCI_DEVFN(HDA1_DEV, HDA1_FUNC)
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/* XHCI */
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#define XHCI_DEV 0x10
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@ -24,11 +253,6 @@
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#define XHCI_DEVID 0x7914
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#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC)
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#define XHCI2_DEV 0x10
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#define XHCI2_FUNC 1
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#define XHCI2_DEVID 0x7814
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#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV, XHCI2_FUNC)
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/* SATA */
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#define SATA_DEV 0x11
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#define SATA_FUNC 0
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@ -37,32 +261,11 @@
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#define AHCI_DEVID_AMD 0x7904
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#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC)
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/* OHCI */
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#define OHCI1_DEV 0x12
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#define OHCI1_FUNC 0
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#define OHCI2_DEV 0x13
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#define OHCI2_FUNC 0
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#define OHCI3_DEV 0x16
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#define OHCI3_FUNC 0
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#define OHCI4_DEV 0x14
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#define OHCI4_FUNC 5
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#define OHCI_DEVID 0x7807
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#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV, OHCI1_FUNC)
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#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV, OHCI2_FUNC)
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#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV, OHCI3_FUNC)
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#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV, OHCI4_FUNC)
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/* EHCI */
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#define EHCI_DEV 0x12
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#define EHCI_FUNC 0
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#define EHCI2_DEV 0x13
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#define EHCI2_FUNC 2
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#define EHCI3_DEV 0x16
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#define EHCI3_FUNC 2
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#define EHCI_DEVID 0x7908
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#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV, EHCI1_FUNC)
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#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV, EHCI2_FUNC)
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#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV, EHCI3_FUNC)
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#define EHCI1_DEVFN PCI_DEVFN(EHCI_DEV, EHCI_FUNC)
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/* SMBUS */
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#define SMBUS_DEV 0x14
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@ -70,20 +273,6 @@
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#define SMBUS_DEVID 0x790b
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#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)
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/* IDE */
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#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)
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#define IDE_DEV 0x14
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#define IDE_FUNC 1
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#define IDE_DEVID 0x780c
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#define IDE_DEVFN PCI_DEVFN(IDE_DEV, IDE_FUNC)
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#endif
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/* HD Audio */
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#define HDA_DEV 0x14
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#define HDA_FUNC 2
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#define HDA_DEVID 0x780d
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#define HDA_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC)
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/* LPC BUS */
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#define PCU_DEV 0x14
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#define LPC_FUNC 3
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@ -96,21 +285,4 @@
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#define SD_DEVID 0x7906
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#define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC)
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/* PCIe Ports */
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#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)
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#define SB_PCIE_DEV 0x15
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#define SB_PCIE_PORT1_FUNC 0
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#define SB_PCIE_PORT2_FUNC 1
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#define SB_PCIE_PORT3_FUNC 2
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#define SB_PCIE_PORT4_FUNC 3
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#define SB_PCIE_PORT1_DEVID 0x7820
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#define SB_PCIE_PORT2_DEVID 0x7821
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#define SB_PCIE_PORT3_DEVID 0x7822
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#define SB_PCIE_PORT4_DEVID 0x7823
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#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT1_FUNC)
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#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT2_FUNC)
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#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT3_FUNC)
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#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT4_FUNC)
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#endif
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#endif /* _PI_STONEYRIDGE_PCI_DEVS_H_ */
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