mb/system76/*: Disable IME by CMOS option
Add CMOS option to set IME mode. Default to "Disable" for CNL and TGL-H, and "Enable" for TGL-U. Not set for KBL, which uses ME_CLEANER. The HECI device must be enabled in devicetree for switching modes to function correctly. Change-Id: I3163dcb0a4af020c2cf6f94f2bb26380f17c253e Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
This commit is contained in:
Tim Crawford
Patrick Georgi
parent
3c01123abb
commit
12a98ffbfb
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@ -1,2 +1,3 @@
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boot_option=Fallback
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debug_level=Debug
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me_state=Disable
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@ -12,10 +12,15 @@ entries
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400 8 r 0 century
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412 4 e 6 debug_level
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416 1 e 2 me_state
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417 3 h 0 me_state_counter
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984 16 h 0 check_sum
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enumerations
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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@ -1,2 +1,3 @@
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boot_option=Fallback
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debug_level=Debug
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me_state=Disable
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@ -12,10 +12,15 @@ entries
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400 8 r 0 century
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412 4 e 6 debug_level
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416 1 e 2 me_state
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417 3 h 0 me_state_counter
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984 16 h 0 check_sum
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enumerations
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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@ -1,2 +1,3 @@
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boot_option=Fallback
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debug_level=Debug
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me_state=Disable
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@ -12,10 +12,15 @@ entries
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400 8 r 0 century
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412 4 e 6 debug_level
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416 1 e 2 me_state
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417 3 h 0 me_state_counter
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984 16 h 0 check_sum
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enumerations
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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@ -1,2 +1,3 @@
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boot_option=Fallback
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debug_level=Debug
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me_state=Enable
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@ -12,10 +12,15 @@ entries
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400 8 r 0 century
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412 4 e 6 debug_level
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416 1 e 2 me_state
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417 3 h 0 me_state_counter
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984 16 h 0 check_sum
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enumerations
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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@ -1,2 +1,3 @@
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boot_option=Fallback
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debug_level=Debug
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me_state=Enable
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@ -12,10 +12,15 @@ entries
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400 8 r 0 century
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412 4 e 6 debug_level
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416 1 e 2 me_state
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417 3 h 0 me_state_counter
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984 16 h 0 check_sum
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enumerations
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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@ -1,2 +1,3 @@
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boot_option=Fallback
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debug_level=Debug
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me_state=Disable
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@ -12,10 +12,15 @@ entries
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400 8 r 0 century
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412 4 e 6 debug_level
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416 1 e 2 me_state
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417 3 h 0 me_state_counter
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984 16 h 0 check_sum
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enumerations
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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@ -1,2 +1,3 @@
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boot_option=Fallback
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debug_level=Debug
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me_state=Disable
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@ -12,10 +12,15 @@ entries
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400 8 r 0 century
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412 4 e 6 debug_level
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416 1 e 2 me_state
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417 3 h 0 me_state_counter
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984 16 h 0 check_sum
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enumerations
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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@ -125,7 +125,9 @@ chip soc/intel/tigerlake
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device i2c 15 on end
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end
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end
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device ref heci1 on end
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device ref heci1 on
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register "HeciEnabled" = "1"
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end
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device ref uart2 on
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# Debug console
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register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
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@ -1,2 +1,3 @@
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boot_option=Fallback
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debug_level=Debug
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me_state=Enable
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@ -12,10 +12,15 @@ entries
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400 8 r 0 century
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412 4 e 6 debug_level
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416 1 e 2 me_state
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417 3 h 0 me_state_counter
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984 16 h 0 check_sum
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enumerations
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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@ -1,2 +1,3 @@
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boot_option=Fallback
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debug_level=Debug
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me_state=Disable
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@ -12,10 +12,15 @@ entries
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400 8 r 0 century
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412 4 e 6 debug_level
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416 1 e 2 me_state
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417 3 h 0 me_state_counter
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984 16 h 0 check_sum
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enumerations
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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@ -1,2 +1,3 @@
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boot_option=Fallback
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debug_level=Debug
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me_state=Disable
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@ -12,10 +12,15 @@ entries
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400 8 r 0 century
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412 4 e 6 debug_level
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416 1 e 2 me_state
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417 3 h 0 me_state_counter
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984 16 h 0 check_sum
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enumerations
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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@ -1,2 +1,3 @@
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boot_option=Fallback
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debug_level=Debug
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me_state=Disable
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@ -12,10 +12,15 @@ entries
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400 8 r 0 century
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412 4 e 6 debug_level
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416 1 e 2 me_state
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417 3 h 0 me_state_counter
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984 16 h 0 check_sum
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enumerations
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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@ -1,2 +1,3 @@
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boot_option=Fallback
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debug_level=Debug
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me_state=Disable
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@ -12,10 +12,15 @@ entries
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400 8 r 0 century
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412 4 e 6 debug_level
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416 1 e 2 me_state
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417 3 h 0 me_state_counter
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984 16 h 0 check_sum
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enumerations
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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@ -160,7 +160,9 @@ chip soc/intel/tigerlake
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device i2c 2c on end
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end
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end
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device ref heci1 on end
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device ref heci1 on
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register "HeciEnabled" = "1"
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end
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device ref uart2 on
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# Debug console
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register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
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@ -1,2 +1,3 @@
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boot_option=Fallback
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debug_level=Debug
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me_state=Disable
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@ -12,10 +12,15 @@ entries
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400 8 r 0 century
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412 4 e 6 debug_level
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416 1 e 2 me_state
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417 3 h 0 me_state_counter
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984 16 h 0 check_sum
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enumerations
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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@ -98,7 +98,7 @@ chip soc/intel/cannonlake
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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