soc/intel: Enable GPIO functions in verstage

Enable GPIO functionality in verstage so platforms can read a
PCH GPIO in verstage to determine recovery mode.

BUG=b:151102807
TEST=make build successful

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I4e3b9da307dcf59ab251d8a6a5e09c2a3cfc59fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39501
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/tigerlake/Makefile.inc

@@ -58,6 +58,7 @@ smm-y += pmutil.c
 smm-y += smihandler.c
 smm-y += uart.c
 
+verstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/tigerlake
 CPPFLAGS_common += -I$(src)/soc/intel/tigerlake/include