src/southbridge: Drop unneeded empty lines
Change-Id: I02aa1e2a9a9061b34b91f832d96123a8595d61b7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Elyes HAOUAS
Michael Niewöhner
parent
b69bbfe1ef
commit
131d9f5190
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@ -81,7 +81,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
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fadt->x_pm1a_cnt_blk.addrh = 0x0;
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fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm_tmr_blk.bit_width = 32;
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fadt->x_pm_tmr_blk.bit_offset = 0;
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@ -89,7 +88,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
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fadt->x_pm_tmr_blk.addrh = 0x0;
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fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */
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fadt->x_gpe0_blk.bit_offset = 0;
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@ -13,7 +13,6 @@
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#include "smbus.h"
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#include "smi.h"
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#define PM_REG_USB_ENABLE 0xef
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enum usb_enable {
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@ -106,7 +105,6 @@ void hudson_enable(struct device *dev)
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}
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}
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static void hudson_init_acpi_ports(void)
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{
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/* We use some of these ports in SMM regardless of whether or not
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@ -7,7 +7,6 @@
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#include <southbridge/amd/common/amd_pci_util.h>
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#include <bootstate.h>
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/*
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* Update the PCI devices with a valid IRQ number
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* that is set in the mainboard PCI_IRQ structures.
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@ -55,5 +55,4 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
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void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
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void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val);
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#endif
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@ -83,7 +83,6 @@ typedef struct _AMD_CONFIG_PARAMS {
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IN OUT unsigned int Reserved[2]; ///< This space is reserved for future use.
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} AMD_CONFIG_PARAMS;
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/// AGESA Binary module header structure
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typedef struct _AMD_IMAGE_HEADER {
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IN unsigned int Signature; ///< Binary Signature
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@ -48,7 +48,6 @@ typedef union _PCI_ADDR {
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#include <OEM.h> /* platform default configuration */
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#include <AMD.h>
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//------------------------------------------------------------------------------------------------------------------------//
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/**
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* SB_CIMx_PARAMETER 0 1 2 Default Value When CIMx Take over
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@ -1,6 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* ACPI - create the Fixed ACPI Description Tables (FADT)
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*/
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@ -112,7 +111,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
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fadt->x_pm2_cnt_blk.addrh = 0x0;
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fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm_tmr_blk.bit_width = 32;
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fadt->x_pm_tmr_blk.bit_offset = 0;
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@ -120,7 +118,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
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fadt->x_pm_tmr_blk.addrh = 0x0;
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fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */
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fadt->x_gpe0_blk.bit_offset = 0;
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@ -39,12 +39,10 @@ void init_sb800_MANUAL_fans(struct device *dev)
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if (sb_chip->fan4_enabled)
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for (i = 0; i < FAN_REGISTER_COUNT; i++)
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pm2_write8(FAN_4_OFFSET + i, sb_chip->fan4_config_vals[i]);
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}
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void init_sb800_IMC_fans(struct device *dev)
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{
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AMDSBCFG sb_config;
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unsigned char *message_ptr;
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int i;
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@ -63,7 +61,6 @@ void init_sb800_IMC_fans(struct device *dev)
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pci_write_config16(dev, 0xA4, sb_chip->imc_port_address | 0x01);
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/*
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* Do an initial manual setup of the fans for things like polarity
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* and frequency.
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@ -107,7 +104,6 @@ if (sb_chip->imc_fan_zone0_enabled) {
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message_ptr = &sb_config.Pecstruct.MSGFun85zone0MSGREG2;
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for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
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*(message_ptr + i) = sb_chip->imc_zone0_fanspeeds[i];
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}
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/*
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@ -138,10 +134,8 @@ if (sb_chip->imc_fan_zone1_enabled) {
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message_ptr = &sb_config.Pecstruct.MSGFun85zone1MSGREG2;
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for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
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*(message_ptr + i) = sb_chip->imc_zone1_fanspeeds[i];
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}
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/*
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********** Zone 2 **********
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*/
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@ -170,7 +164,6 @@ if (sb_chip->imc_fan_zone2_enabled) {
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message_ptr = &sb_config.Pecstruct.MSGFun85zone2MSGREG2;
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for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
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*(message_ptr + i) = sb_chip->imc_zone2_fanspeeds[i];
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}
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/*
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@ -202,7 +195,6 @@ if (sb_chip->imc_fan_zone3_enabled) {
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message_ptr = &sb_config.Pecstruct.MSGFun85zone3MSGREG2;
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for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
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*(message_ptr + i) = sb_chip->imc_zone3_fanspeeds[i];
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}
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/*
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@ -70,7 +70,6 @@ void init_sb800_MANUAL_fans(struct device *dev);
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#define FREQ_14HZ 0xFE
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#define FREQ_11HZ 0xFF
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/* IMC Fan Control Definitions */
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#define IMC_MODE1_FAN_ENABLED ( 1 << 0 )
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#define IMC_MODE1_FAN_IMC_CONTROLLED ( 1 << 2 )
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@ -213,7 +213,6 @@ static const struct pci_driver usb_ohci4_driver __pci_driver = {
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.device = PCI_DEVICE_ID_ATI_SB800_USB_20_5, /* OHCI-USB4 */
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};
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static struct device_operations azalia_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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@ -227,7 +226,6 @@ static const struct pci_driver azalia_driver __pci_driver = {
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.device = PCI_DEVICE_ID_ATI_SB800_HDA,
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};
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static struct device_operations gec_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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@ -358,7 +356,6 @@ static void sb800_enable(struct device *dev)
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}
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break;
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case PCI_DEVFN(0x14, 3): /* 0:14:3 LPC */
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/* Initialize the fans */
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#if CONFIG(SB800_IMC_FAN_CONTROL)
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@ -1,6 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _CIMX_H_
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#define _CIMX_H_
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@ -1,6 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/io.h>
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#include "smbus.h"
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#include <console/console.h> /* printk */
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@ -105,7 +105,6 @@ static void ImcSleep(void)
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WaitForEcLDN9MailboxCmdAck();
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}
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static void ImcWakeup(void)
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{
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u8 cmd_val = 0x96; /* Kick off IMC Mailbox command 96 */
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@ -1,6 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _AMD_SB_DEFS_H_
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#define _AMD_SB_DEFS_H_
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@ -83,7 +83,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
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fadt->x_pm1a_cnt_blk.addrh = 0x0;
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fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm_tmr_blk.bit_width = 32;
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fadt->x_pm_tmr_blk.bit_offset = 0;
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@ -91,7 +90,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
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fadt->x_pm_tmr_blk.addrh = 0x0;
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fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */
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fadt->x_gpe0_blk.bit_offset = 0;
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@ -55,5 +55,4 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
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void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
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void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val);
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#endif
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@ -202,7 +202,6 @@ int intel_early_me_init_done(u8 status)
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timestamp_add_now(TS_ME_INFORM_DRAM_DONE);
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}
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me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
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printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2);
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printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", me_fws2 & 0x1);
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@ -220,7 +219,6 @@ int intel_early_me_init_done(u8 status)
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printk(BIOS_NOTICE, "ME: Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24);
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printk(BIOS_NOTICE, "ME: Progress code : 0x%x\n", (me_fws2 & 0xf0000000) >> 28);
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/* Return the requested BIOS action */
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printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n",
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me_ack_values[(hfs & 0xe) >> 1]);
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@ -13,7 +13,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
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int c2_latency;
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fadt->sci_int = 0x9;
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if (permanent_smi_handler()) {
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@ -734,7 +734,6 @@ static struct device_operations device_ops = {
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.ops_pci = &pci_dev_ops_pci,
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};
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/* IDs for LPC device of Intel 6 Series Chipset, Intel 7 Series Chipset, and
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* Intel C200 Series Chipset
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*/
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@ -197,7 +197,6 @@ struct me_fw_version {
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u16 recovery_hot_fix;
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} __packed;
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#define HECI_EOP_STATUS_SUCCESS 0x0
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#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
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@ -142,7 +142,6 @@ void southbridge_smi_monitor(void)
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mask |= (0xff << ((i - 16) << 2));
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}
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/* IOTRAP(3) SMI function call */
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if (IOTRAP(3)) {
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if (gnvs && gnvs->smif)
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@ -94,7 +94,6 @@ void dump_smi_status(u32 smi_sts)
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printk(BIOS_DEBUG, "\n");
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}
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/**
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* @brief read and clear GPE0_STS
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* @return GPE0_STS register
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@ -158,7 +157,6 @@ u32 reset_tco_status(void)
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return reg32;
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}
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void dump_tco_status(u32 tco_sts)
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{
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printk(BIOS_DEBUG, "TCO_STS: ");
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@ -190,7 +188,6 @@ void smi_set_eos(void)
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write_pmbase8(SMI_EN, reg8);
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}
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void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
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{
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int i;
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@ -27,7 +27,6 @@
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#define GPI_IS_SCI 0x02
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#define GPI_IS_NMI 0x03
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#define MAINBOARD_POWER_OFF 0
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#define MAINBOARD_POWER_ON 1
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#define MAINBOARD_POWER_KEEP 2
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@ -1,6 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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#include <device/pci.h>
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#include <console/console.h>
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@ -95,7 +95,6 @@ __weak void southbridge_smm_xhci_sleep(u8 slp_type)
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{
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}
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static void southbridge_smi_sleep(void)
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{
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u8 reg8;
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@ -388,8 +387,6 @@ static void southbridge_smi_mc(void)
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printk(BIOS_DEBUG, "Microcontroller SMI.\n");
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}
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static void southbridge_smi_tco(void)
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{
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u32 tco_sts;
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@ -718,7 +718,6 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
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return 0;
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}
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static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset,
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size_t len)
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{
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@ -92,7 +92,6 @@ static void pwrmgt_read_resources(struct device *dev)
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IORESOURCE_RESERVE;
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}
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static const struct smbus_bus_operations lops_smbus_bus = {
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};
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@ -33,7 +33,6 @@
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#define MBAR 0x14
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#define SEC_CODEC 0x40
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/* FIXME. This table is probably mainboard specific */
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static u16 ac97_function[16*2][4] = {
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{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
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@ -20,7 +20,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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{
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u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe;
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fadt->sci_int = 0x9;
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if (permanent_smi_handler()) {
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@ -46,8 +46,6 @@ void aseg_smm_lock(void);
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/* IDE_TIM bits */
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#define IDE_DECODE_ENABLE (1 << 15)
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#define PCI_DMA_CFG 0x90
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#define SERIRQ_CNTL 0x64
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#define GEN_CNTL 0xd0
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@ -93,7 +91,6 @@ void aseg_smm_lock(void);
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#define RTC_FAILED (1 <<2)
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#define PM1_STS 0x00
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#define WAK_STS (1 << 15)
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#define PCIEXPWAK_STS (1 << 14)
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@ -1,6 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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#include <device/pci.h>
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#include <console/console.h>
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@ -13,7 +12,6 @@
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#include <string.h>
|
||||
#include "i82801dx.h"
|
||||
|
||||
|
||||
void northbridge_write_smram(u8 smram);
|
||||
|
||||
/* For intel/e7505. */
|
||||
|
|
@ -98,7 +96,6 @@ static void dump_smi_status(u32 smi_sts)
|
|||
printk(BIOS_DEBUG, "\n");
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief read and clear GPE0_STS
|
||||
* @return GPE0_STS register
|
||||
|
|
@ -138,7 +135,6 @@ static void dump_gpe0_status(u32 gpe0_sts)
|
|||
printk(BIOS_DEBUG, "\n");
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief read and clear ALT_GP_SMI_STS
|
||||
* @return ALT_GP_SMI_STS register
|
||||
|
|
@ -164,8 +160,6 @@ static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
|
|||
printk(BIOS_DEBUG, "\n");
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief read and clear TCOx_STS
|
||||
* @return TCOx_STS registers
|
||||
|
|
@ -184,7 +178,6 @@ static u32 reset_tco_status(void)
|
|||
return reg32;
|
||||
}
|
||||
|
||||
|
||||
static void dump_tco_status(u32 tco_sts)
|
||||
{
|
||||
printk(BIOS_DEBUG, "TCO_STS: ");
|
||||
|
|
@ -204,8 +197,6 @@ static void dump_tco_status(u32 tco_sts)
|
|||
printk(BIOS_DEBUG, "\n");
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Set the EOS bit
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -96,7 +96,6 @@ static void dump_smi_status(u32 smi_sts)
|
|||
printk(BIOS_DEBUG, "\n");
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief read and clear GPE0_STS
|
||||
* @return GPE0_STS register
|
||||
|
|
@ -136,7 +135,6 @@ static void dump_gpe0_status(u32 gpe0_sts)
|
|||
printk(BIOS_DEBUG, "\n");
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief read and clear TCOx_STS
|
||||
* @return TCOx_STS registers
|
||||
|
|
@ -155,7 +153,6 @@ static u32 reset_tco_status(void)
|
|||
return reg32;
|
||||
}
|
||||
|
||||
|
||||
static void dump_tco_status(u32 tco_sts)
|
||||
{
|
||||
printk(BIOS_DEBUG, "TCO_STS: ");
|
||||
|
|
@ -222,7 +219,6 @@ static void busmaster_disable_on_bus(int bus)
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
static void southbridge_smi_sleep(void)
|
||||
{
|
||||
u8 reg8;
|
||||
|
|
@ -389,8 +385,6 @@ static void southbridge_smi_mc(void)
|
|||
printk(BIOS_DEBUG, "Microcontroller SMI.\n");
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void southbridge_smi_tco(void)
|
||||
{
|
||||
u32 tco_sts;
|
||||
|
|
|
|||
|
|
@ -34,7 +34,6 @@
|
|||
#define MBAR 0x14
|
||||
#define SEC_CODEC 0x40
|
||||
|
||||
|
||||
/* FIXME. This table is probably mainboard specific */
|
||||
static u16 ac97_function[16*2][4] = {
|
||||
{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
|
||||
|
|
|
|||
|
|
@ -411,7 +411,6 @@ unsigned long acpi_fill_madt(unsigned long current)
|
|||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL);
|
||||
|
||||
|
||||
return current;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -58,7 +58,6 @@ static int lsmbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buf)
|
|||
return do_smbus_block_read(res->base, device, cmd, bytes, buf);
|
||||
}
|
||||
|
||||
|
||||
static struct smbus_bus_operations lops_smbus_bus = {
|
||||
.read_byte = lsmbus_read_byte,
|
||||
.write_byte = lsmbus_write_byte,
|
||||
|
|
|
|||
|
|
@ -58,7 +58,6 @@ void southbridge_smi_monitor(void)
|
|||
mask |= (0xff << ((i - 16) << 2));
|
||||
}
|
||||
|
||||
|
||||
/* IOTRAP(3) SMI function call */
|
||||
if (IOTRAP(3)) {
|
||||
if (gnvs && gnvs->smif)
|
||||
|
|
|
|||
|
|
@ -38,7 +38,6 @@ void i82801ix_dmi_setup(void)
|
|||
RCBA8(RCBA_BCR) = 0x45;
|
||||
RCBA32(RCBA_CIR6) &= ~(1 << 7);
|
||||
|
||||
|
||||
/* VC1 setup for isochronous transfers: */
|
||||
|
||||
/* Set VC1 virtual channel id to 1. */
|
||||
|
|
@ -60,7 +59,6 @@ void i82801ix_dmi_setup(void)
|
|||
/* Enable VC1. */
|
||||
RCBA32(RCBA_V1CTL) |= (1 << 31);
|
||||
|
||||
|
||||
/* Setup RCRB: */
|
||||
|
||||
/* Set component id to 2 for southbridge, northbridge has id 1. */
|
||||
|
|
|
|||
|
|
@ -20,11 +20,8 @@
|
|||
#define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60)
|
||||
#define DEFAULT_GPIOBASE 0x00000580
|
||||
|
||||
|
||||
#define APM_CNT 0xb2
|
||||
|
||||
|
||||
|
||||
#define GP_IO_USE_SEL 0x00
|
||||
#define GP_IO_SEL 0x04
|
||||
#define GP_LVL 0x0c
|
||||
|
|
@ -73,23 +70,19 @@
|
|||
#define D31F0_CxSTATE_CNF 0xa9
|
||||
#define D31F0_C4TIMING_CNT 0xaa
|
||||
|
||||
|
||||
/* D31:F2 SATA */
|
||||
#define D31F2_IDE_TIM_PRI 0x40
|
||||
#define D31F2_IDE_TIM_SEC 0x42
|
||||
#define D31F2_SIDX 0xa0
|
||||
#define D31F2_SDAT 0xa4
|
||||
|
||||
|
||||
/* D30:F0 PCI-to-PCI bridge */
|
||||
#define D30F0_SMLT 0x1b
|
||||
|
||||
|
||||
/* D28:F0-5 PCIe root ports */
|
||||
#define D28Fx_XCAP 0x42
|
||||
#define D28Fx_SLCAP 0x54
|
||||
|
||||
|
||||
/* PCI Configuration Space (D31:F3): SMBus */
|
||||
#define SMB_BASE 0x20
|
||||
#define HOSTC 0x40
|
||||
|
|
@ -154,7 +147,6 @@
|
|||
#define FD_SD (1 << 3) /* SMBus */
|
||||
#define FD_SAD1 (1 << 2) /* SATA #1 */
|
||||
|
||||
|
||||
#ifndef __ACPI__
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
|
|
|
|||
|
|
@ -114,7 +114,6 @@ static void aseg_smm_install(void)
|
|||
return;
|
||||
smm_handler_copied = 1;
|
||||
|
||||
|
||||
/* if we're resuming from S3, the SMM code is already in place,
|
||||
* so don't copy it again to keep the current SMM state */
|
||||
|
||||
|
|
|
|||
|
|
@ -51,7 +51,6 @@ void southbridge_smi_monitor(void)
|
|||
mask |= (0xff << ((i - 16) << 3));
|
||||
}
|
||||
|
||||
|
||||
/* IOTRAP(3) SMI function call */
|
||||
if (IOTRAP(3)) {
|
||||
if (gnvs && gnvs->smif)
|
||||
|
|
|
|||
|
|
@ -11,11 +11,8 @@
|
|||
#define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60)
|
||||
#define DEFAULT_GPIOBASE 0x00000580
|
||||
|
||||
|
||||
#define APM_CNT 0xb2
|
||||
|
||||
|
||||
|
||||
#define GP_IO_USE_SEL 0x00
|
||||
#define GP_IO_SEL 0x04
|
||||
#define GP_LVL 0x0c
|
||||
|
|
@ -66,23 +63,19 @@
|
|||
#define D31F0_C4TIMING_CNT 0xaa
|
||||
#define D31F0_GPIO_ROUT 0xb8
|
||||
|
||||
|
||||
/* D31:F2 SATA */
|
||||
#define D31F2_IDE_TIM_PRI 0x40
|
||||
#define D31F2_IDE_TIM_SEC 0x42
|
||||
#define D31F2_SIDX 0xa0
|
||||
#define D31F2_SDAT 0xa4
|
||||
|
||||
|
||||
/* D30:F0 PCI-to-PCI bridge */
|
||||
#define D30F0_SMLT 0x1b
|
||||
|
||||
|
||||
/* D28:F0-5 PCIe root ports */
|
||||
#define D28Fx_XCAP 0x42
|
||||
#define D28Fx_SLCAP 0x54
|
||||
|
||||
|
||||
/* PCI Configuration Space (D31:F3): SMBus */
|
||||
#define SMB_BASE 0x20
|
||||
#define HOSTC 0x40
|
||||
|
|
@ -164,7 +157,6 @@
|
|||
#define FD_SD (1 << 3) /* SMBus */
|
||||
#define FD_SAD1 (1 << 2) /* SATA #1 */
|
||||
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
#include <device/pci_ops.h>
|
||||
|
|
|
|||
|
|
@ -408,7 +408,6 @@ unsigned long acpi_fill_madt(unsigned long current)
|
|||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL);
|
||||
|
||||
|
||||
return current;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -52,7 +52,6 @@ void southbridge_smi_monitor(void)
|
|||
mask |= (0xff << ((i - 16) << 3));
|
||||
}
|
||||
|
||||
|
||||
/* IOTRAP(3) SMI function call */
|
||||
if (IOTRAP(3)) {
|
||||
if (gnvs && gnvs->smif)
|
||||
|
|
|
|||
|
|
@ -74,7 +74,6 @@ static void early_lpc_init(void)
|
|||
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
|
||||
}
|
||||
|
||||
|
||||
void bootblock_early_southbridge_init(void)
|
||||
{
|
||||
enable_spi_prefetching_and_caching();
|
||||
|
|
|
|||
|
|
@ -13,7 +13,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
|
|||
u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
|
||||
int c2_latency;
|
||||
|
||||
|
||||
fadt->sci_int = 0x9;
|
||||
|
||||
if (permanent_smi_handler()) {
|
||||
|
|
|
|||
|
|
@ -618,7 +618,6 @@ static struct device_operations device_ops = {
|
|||
.ops_pci = &pci_dev_ops_pci,
|
||||
};
|
||||
|
||||
|
||||
static const unsigned short pci_device_ids[] = {
|
||||
PCI_DID_INTEL_IBEXPEAK_LPC_QM57,
|
||||
PCI_DID_INTEL_IBEXPEAK_LPC_HM55,
|
||||
|
|
|
|||
|
|
@ -604,7 +604,6 @@ static const unsigned short pci_device_ids[] = {
|
|||
0
|
||||
};
|
||||
|
||||
|
||||
static const struct pci_driver intel_me __pci_driver = {
|
||||
.ops = &device_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
|
|
|
|||
|
|
@ -198,7 +198,6 @@ struct me_fw_version {
|
|||
u16 recovery_hot_fix;
|
||||
} __packed;
|
||||
|
||||
|
||||
#define HECI_EOP_STATUS_SUCCESS 0x0
|
||||
#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
|
||||
|
||||
|
|
|
|||
|
|
@ -107,7 +107,6 @@ void southbridge_smi_monitor(void)
|
|||
mask |= (0xff << ((i - 16) << 2));
|
||||
}
|
||||
|
||||
|
||||
/* IOTRAP(3) SMI function call */
|
||||
if (IOTRAP(3)) {
|
||||
if (gnvs && gnvs->smif)
|
||||
|
|
|
|||
|
|
@ -66,7 +66,6 @@ static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
|
|||
pci_write_config8(dev, 0x80, access_cntl);
|
||||
}
|
||||
|
||||
|
||||
static struct pci_operations lops_pci = {
|
||||
.set_subsystem = &usb_ehci_set_subsystem,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -91,5 +91,4 @@ struct southbridge_intel_lynxpoint_config {
|
|||
bool docking_supported;
|
||||
};
|
||||
|
||||
|
||||
#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */
|
||||
|
|
|
|||
|
|
@ -19,7 +19,6 @@ static u16 get_gpio_base(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* This function will return a number that indicates which PIRQ
|
||||
* this GPIO maps to. If this is not a PIRQ capable GPIO then
|
||||
|
|
|
|||
|
|
@ -791,7 +791,6 @@ static struct device_operations device_ops = {
|
|||
.ops_pci = &pci_dev_ops_pci,
|
||||
};
|
||||
|
||||
|
||||
/* IDs for LPC device of Intel 8 Series Chipset (Lynx Point) */
|
||||
static const unsigned short pci_device_ids[] = {
|
||||
0x8c41, /* Mobile Full Featured Engineering Sample. */
|
||||
|
|
|
|||
|
|
@ -57,7 +57,6 @@ static void print_gpio_status(u32 status, int start)
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* PM1_CNT
|
||||
*/
|
||||
|
|
@ -78,7 +77,6 @@ void disable_pm1_control(u32 mask)
|
|||
outl(pm1_cnt, get_pmbase() + PM1_CNT);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* PM1
|
||||
*/
|
||||
|
|
@ -127,7 +125,6 @@ void enable_pm1(u16 events)
|
|||
outw(events, get_pmbase() + PM1_EN);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* SMI
|
||||
*/
|
||||
|
|
@ -198,7 +195,6 @@ void disable_smi(u32 mask)
|
|||
outl(smi_en, get_pmbase() + SMI_EN);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* ALT_GP_SMI
|
||||
*/
|
||||
|
|
@ -298,7 +294,6 @@ void enable_alt_smi(u32 mask)
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* TCO
|
||||
*/
|
||||
|
|
@ -368,7 +363,6 @@ void enable_tco_sci(void)
|
|||
enable_gpe(TCOSCI_EN);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* GPE0
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -78,7 +78,6 @@ static void busmaster_disable_on_bus(int bus)
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
static void southbridge_smi_sleep(void)
|
||||
{
|
||||
u8 reg8;
|
||||
|
|
@ -379,8 +378,6 @@ static void southbridge_smi_mc(void)
|
|||
printk(BIOS_DEBUG, "Microcontroller SMI.\n");
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void southbridge_smi_tco(void)
|
||||
{
|
||||
u32 tco_sts = clear_tco_status();
|
||||
|
|
@ -443,7 +440,6 @@ static void southbridge_smi_monitor(void)
|
|||
mask |= (0xff << ((i - 16) << 2));
|
||||
}
|
||||
|
||||
|
||||
/* IOTRAP(3) SMI function call */
|
||||
if (IOTRAP(3)) {
|
||||
if (gnvs && gnvs->smif)
|
||||
|
|
|
|||
|
|
@ -107,11 +107,9 @@ static void rl5c476_init(struct device *dev)
|
|||
pc16->moffl0 = 0;
|
||||
pc16->moffh0 = 0x40;
|
||||
|
||||
|
||||
/* set I/O width for Auto Data width */
|
||||
pc16->ioctrl = 0x22;
|
||||
|
||||
|
||||
/* enable I/O window 0 and 1 */
|
||||
pc16->awinen = 0xc1;
|
||||
|
||||
|
|
@ -125,7 +123,6 @@ static void rl5c476_init(struct device *dev)
|
|||
|
||||
pc16->igctrl = 0x69;
|
||||
|
||||
|
||||
/* 16 bit CF always have first config byte at 0x200 into
|
||||
* Config structure, but CF+ may not according to spec -
|
||||
* should locate through reading tuple data, but this should
|
||||
|
|
|
|||
|
|
@ -2,10 +2,8 @@
|
|||
|
||||
/* rl5c476 routines and defines*/
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
/* the 16 bit control structure for ricoh cardbus bridge */
|
||||
typedef struct pc16reg {
|
||||
u8 idrevs;
|
||||
|
|
|
|||
Loading…
Reference in New Issue