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src/southbridge: Drop unneeded empty lines 

Change-Id: I02aa1e2a9a9061b34b91f832d96123a8595d61b7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Elyes HAOUAS 2020-08-19 21:40:21 +02:00 committed by Michael Niewöhner
parent b69bbfe1ef
commit 131d9f5190
57 changed files with 0 additions and 117 deletions
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2
src/southbridge/amd/agesa/hudson/fadt.c
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@ -81,7 +81,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
fadt->x_pm1a_cnt_blk.addrh = 0x0; fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.bit_offset = 0;
@ -89,7 +88,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
fadt->x_pm_tmr_blk.addrh = 0x0; fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */
fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.bit_offset = 0;

2
src/southbridge/amd/agesa/hudson/hudson.c
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@ -13,7 +13,6 @@
#include "smbus.h" #include "smbus.h"
#include "smi.h" #include "smi.h"
#define PM_REG_USB_ENABLE 0xef #define PM_REG_USB_ENABLE 0xef
enum usb_enable { enum usb_enable {
@ -106,7 +105,6 @@ void hudson_enable(struct device *dev)
} }
} }
static void hudson_init_acpi_ports(void) static void hudson_init_acpi_ports(void)
{ {
/* We use some of these ports in SMM regardless of whether or not /* We use some of these ports in SMM regardless of whether or not

1
src/southbridge/amd/agesa/hudson/pci.c
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@ -7,7 +7,6 @@
#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/common/amd_pci_util.h>
#include <bootstate.h> #include <bootstate.h>
/* /*
* Update the PCI devices with a valid IRQ number * Update the PCI devices with a valid IRQ number
* that is set in the mainboard PCI_IRQ structures. * that is set in the mainboard PCI_IRQ structures.

1
src/southbridge/amd/agesa/hudson/smbus.h
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@ -55,5 +55,4 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val); void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val);
#endif #endif

1
src/southbridge/amd/cimx/sb800/Amd.h
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@ -83,7 +83,6 @@ typedef struct _AMD_CONFIG_PARAMS {
IN OUT unsigned int Reserved[2]; ///< This space is reserved for future use. IN OUT unsigned int Reserved[2]; ///< This space is reserved for future use.
} AMD_CONFIG_PARAMS; } AMD_CONFIG_PARAMS;
/// AGESA Binary module header structure /// AGESA Binary module header structure
typedef struct _AMD_IMAGE_HEADER { typedef struct _AMD_IMAGE_HEADER {
IN unsigned int Signature; ///< Binary Signature IN unsigned int Signature; ///< Binary Signature

1
src/southbridge/amd/cimx/sb800/SBPLATFORM.h
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@ -48,7 +48,6 @@ typedef union _PCI_ADDR {
#include <OEM.h> /* platform default configuration */ #include <OEM.h> /* platform default configuration */
#include <AMD.h> #include <AMD.h>
//------------------------------------------------------------------------------------------------------------------------// //------------------------------------------------------------------------------------------------------------------------//
/** /**
* SB_CIMx_PARAMETER 0 1 2 Default Value When CIMx Take over * SB_CIMx_PARAMETER 0 1 2 Default Value When CIMx Take over

3
src/southbridge/amd/cimx/sb800/fadt.c
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@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* /*
* ACPI - create the Fixed ACPI Description Tables (FADT) * ACPI - create the Fixed ACPI Description Tables (FADT)
*/ */
@ -112,7 +111,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS; fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
fadt->x_pm2_cnt_blk.addrh = 0x0; fadt->x_pm2_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.bit_offset = 0;
@ -120,7 +118,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS; fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
fadt->x_pm_tmr_blk.addrh = 0x0; fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */
fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.bit_offset = 0;

8
src/southbridge/amd/cimx/sb800/fan.c
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@ -39,12 +39,10 @@ void init_sb800_MANUAL_fans(struct device *dev)
if (sb_chip->fan4_enabled) if (sb_chip->fan4_enabled)
for (i = 0; i < FAN_REGISTER_COUNT; i++) for (i = 0; i < FAN_REGISTER_COUNT; i++)
pm2_write8(FAN_4_OFFSET + i, sb_chip->fan4_config_vals[i]); pm2_write8(FAN_4_OFFSET + i, sb_chip->fan4_config_vals[i]);
} }
void init_sb800_IMC_fans(struct device *dev) void init_sb800_IMC_fans(struct device *dev)
{ {
AMDSBCFG sb_config; AMDSBCFG sb_config;
unsigned char *message_ptr; unsigned char *message_ptr;
int i; int i;
@ -63,7 +61,6 @@ void init_sb800_IMC_fans(struct device *dev)
pci_write_config16(dev, 0xA4, sb_chip->imc_port_address | 0x01); pci_write_config16(dev, 0xA4, sb_chip->imc_port_address | 0x01);
/* /*
* Do an initial manual setup of the fans for things like polarity * Do an initial manual setup of the fans for things like polarity
* and frequency. * and frequency.
@ -107,7 +104,6 @@ if (sb_chip->imc_fan_zone0_enabled) {
message_ptr = &sb_config.Pecstruct.MSGFun85zone0MSGREG2; message_ptr = &sb_config.Pecstruct.MSGFun85zone0MSGREG2;
for (i = 0; i < IMC_FAN_SPEED_COUNT; i++) for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone0_fanspeeds[i]; *(message_ptr + i) = sb_chip->imc_zone0_fanspeeds[i];
} }
/* /*
@ -138,10 +134,8 @@ if (sb_chip->imc_fan_zone1_enabled) {
message_ptr = &sb_config.Pecstruct.MSGFun85zone1MSGREG2; message_ptr = &sb_config.Pecstruct.MSGFun85zone1MSGREG2;
for (i = 0; i < IMC_FAN_SPEED_COUNT; i++) for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone1_fanspeeds[i]; *(message_ptr + i) = sb_chip->imc_zone1_fanspeeds[i];
} }
/* /*
********** Zone 2 ********** ********** Zone 2 **********
*/ */
@ -170,7 +164,6 @@ if (sb_chip->imc_fan_zone2_enabled) {
message_ptr = &sb_config.Pecstruct.MSGFun85zone2MSGREG2; message_ptr = &sb_config.Pecstruct.MSGFun85zone2MSGREG2;
for (i = 0; i < IMC_FAN_SPEED_COUNT; i++) for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone2_fanspeeds[i]; *(message_ptr + i) = sb_chip->imc_zone2_fanspeeds[i];
} }
/* /*
@ -202,7 +195,6 @@ if (sb_chip->imc_fan_zone3_enabled) {
message_ptr = &sb_config.Pecstruct.MSGFun85zone3MSGREG2; message_ptr = &sb_config.Pecstruct.MSGFun85zone3MSGREG2;
for (i = 0; i < IMC_FAN_SPEED_COUNT; i++) for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone3_fanspeeds[i]; *(message_ptr + i) = sb_chip->imc_zone3_fanspeeds[i];
} }
/* /*

1
src/southbridge/amd/cimx/sb800/fan.h
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@ -70,7 +70,6 @@ void init_sb800_MANUAL_fans(struct device *dev);
#define FREQ_14HZ 0xFE #define FREQ_14HZ 0xFE
#define FREQ_11HZ 0xFF #define FREQ_11HZ 0xFF
/* IMC Fan Control Definitions */ /* IMC Fan Control Definitions */
#define IMC_MODE1_FAN_ENABLED ( 1 << 0 ) #define IMC_MODE1_FAN_ENABLED ( 1 << 0 )
#define IMC_MODE1_FAN_IMC_CONTROLLED ( 1 << 2 ) #define IMC_MODE1_FAN_IMC_CONTROLLED ( 1 << 2 )

3
src/southbridge/amd/cimx/sb800/late.c
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@ -213,7 +213,6 @@ static const struct pci_driver usb_ohci4_driver __pci_driver = {
.device = PCI_DEVICE_ID_ATI_SB800_USB_20_5, /* OHCI-USB4 */ .device = PCI_DEVICE_ID_ATI_SB800_USB_20_5, /* OHCI-USB4 */
}; };
static struct device_operations azalia_ops = { static struct device_operations azalia_ops = {
.read_resources = pci_dev_read_resources, .read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
@ -227,7 +226,6 @@ static const struct pci_driver azalia_driver __pci_driver = {
.device = PCI_DEVICE_ID_ATI_SB800_HDA, .device = PCI_DEVICE_ID_ATI_SB800_HDA,
}; };
static struct device_operations gec_ops = { static struct device_operations gec_ops = {
.read_resources = pci_dev_read_resources, .read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
@ -358,7 +356,6 @@ static void sb800_enable(struct device *dev)
} }
break; break;
case PCI_DEVFN(0x14, 3): /* 0:14:3 LPC */ case PCI_DEVFN(0x14, 3): /* 0:14:3 LPC */
/* Initialize the fans */ /* Initialize the fans */
#if CONFIG(SB800_IMC_FAN_CONTROL) #if CONFIG(SB800_IMC_FAN_CONTROL)

1
src/southbridge/amd/cimx/sb800/sb_cimx.h
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@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _CIMX_H_ #ifndef _CIMX_H_
#define _CIMX_H_ #define _CIMX_H_

1
src/southbridge/amd/cimx/sb800/smbus.c
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@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/io.h> #include <arch/io.h>
#include "smbus.h" #include "smbus.h"
#include <console/console.h> /* printk */ #include <console/console.h> /* printk */

1
src/southbridge/amd/cimx/sb800/spi.c
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@ -105,7 +105,6 @@ static void ImcSleep(void)
WaitForEcLDN9MailboxCmdAck(); WaitForEcLDN9MailboxCmdAck();
} }
static void ImcWakeup(void) static void ImcWakeup(void)
{ {
u8 cmd_val = 0x96; /* Kick off IMC Mailbox command 96 */ u8 cmd_val = 0x96; /* Kick off IMC Mailbox command 96 */

1
src/southbridge/amd/common/amd_defs.h
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@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _AMD_SB_DEFS_H_ #ifndef _AMD_SB_DEFS_H_
#define _AMD_SB_DEFS_H_ #define _AMD_SB_DEFS_H_

2
src/southbridge/amd/pi/hudson/fadt.c
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@ -83,7 +83,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
fadt->x_pm1a_cnt_blk.addrh = 0x0; fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.bit_offset = 0;
@ -91,7 +90,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
fadt->x_pm_tmr_blk.addrh = 0x0; fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */
fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.bit_offset = 0;

1
src/southbridge/amd/pi/hudson/smbus.h
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@ -55,5 +55,4 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val); void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val);
#endif #endif

2
src/southbridge/intel/bd82x6x/early_me.c
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@ -202,7 +202,6 @@ int intel_early_me_init_done(u8 status)
timestamp_add_now(TS_ME_INFORM_DRAM_DONE); timestamp_add_now(TS_ME_INFORM_DRAM_DONE);
} }
me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48); me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2); printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2);
printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", me_fws2 & 0x1); printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", me_fws2 & 0x1);
@ -220,7 +219,6 @@ int intel_early_me_init_done(u8 status)
printk(BIOS_NOTICE, "ME: Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24); printk(BIOS_NOTICE, "ME: Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24);
printk(BIOS_NOTICE, "ME: Progress code : 0x%x\n", (me_fws2 & 0xf0000000) >> 28); printk(BIOS_NOTICE, "ME: Progress code : 0x%x\n", (me_fws2 & 0xf0000000) >> 28);
/* Return the requested BIOS action */ /* Return the requested BIOS action */
printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n", printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n",
me_ack_values[(hfs & 0xe) >> 1]); me_ack_values[(hfs & 0xe) >> 1]);

1
src/southbridge/intel/bd82x6x/fadt.c
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@ -13,7 +13,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
int c2_latency; int c2_latency;
fadt->sci_int = 0x9; fadt->sci_int = 0x9;
if (permanent_smi_handler()) { if (permanent_smi_handler()) {

1
src/southbridge/intel/bd82x6x/lpc.c
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@ -734,7 +734,6 @@ static struct device_operations device_ops = {
.ops_pci = &pci_dev_ops_pci, .ops_pci = &pci_dev_ops_pci,
}; };
/* IDs for LPC device of Intel 6 Series Chipset, Intel 7 Series Chipset, and /* IDs for LPC device of Intel 6 Series Chipset, Intel 7 Series Chipset, and
* Intel C200 Series Chipset * Intel C200 Series Chipset
*/ */

1
src/southbridge/intel/bd82x6x/me.h
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@ -197,7 +197,6 @@ struct me_fw_version {
u16 recovery_hot_fix; u16 recovery_hot_fix;
} __packed; } __packed;
#define HECI_EOP_STATUS_SUCCESS 0x0 #define HECI_EOP_STATUS_SUCCESS 0x0
#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1

1
src/southbridge/intel/bd82x6x/smihandler.c
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@ -142,7 +142,6 @@ void southbridge_smi_monitor(void)
mask |= (0xff << ((i - 16) << 2)); mask |= (0xff << ((i - 16) << 2));
} }
/* IOTRAP(3) SMI function call */ /* IOTRAP(3) SMI function call */
if (IOTRAP(3)) { if (IOTRAP(3)) {
if (gnvs && gnvs->smif) if (gnvs && gnvs->smif)

3
src/southbridge/intel/common/pmutil.c
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@ -94,7 +94,6 @@ void dump_smi_status(u32 smi_sts)
printk(BIOS_DEBUG, "\n"); printk(BIOS_DEBUG, "\n");
} }
/** /**
* @brief read and clear GPE0_STS * @brief read and clear GPE0_STS
* @return GPE0_STS register * @return GPE0_STS register
@ -158,7 +157,6 @@ u32 reset_tco_status(void)
return reg32; return reg32;
} }
void dump_tco_status(u32 tco_sts) void dump_tco_status(u32 tco_sts)
{ {
printk(BIOS_DEBUG, "TCO_STS: "); printk(BIOS_DEBUG, "TCO_STS: ");
@ -190,7 +188,6 @@ void smi_set_eos(void)
write_pmbase8(SMI_EN, reg8); write_pmbase8(SMI_EN, reg8);
} }
void dump_alt_gp_smi_status(u16 alt_gp_smi_sts) void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
{ {
int i; int i;

1
src/southbridge/intel/common/pmutil.h
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@ -27,7 +27,6 @@
#define GPI_IS_SCI 0x02 #define GPI_IS_SCI 0x02
#define GPI_IS_NMI 0x03 #define GPI_IS_NMI 0x03
#define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_OFF 0
#define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_ON 1
#define MAINBOARD_POWER_KEEP 2 #define MAINBOARD_POWER_KEEP 2

1
src/southbridge/intel/common/smi.c
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@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <console/console.h> #include <console/console.h>

3
src/southbridge/intel/common/smihandler.c
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@ -95,7 +95,6 @@ __weak void southbridge_smm_xhci_sleep(u8 slp_type)
{ {
} }
static void southbridge_smi_sleep(void) static void southbridge_smi_sleep(void)
{ {
u8 reg8; u8 reg8;
@ -388,8 +387,6 @@ static void southbridge_smi_mc(void)
printk(BIOS_DEBUG, "Microcontroller SMI.\n"); printk(BIOS_DEBUG, "Microcontroller SMI.\n");
} }
static void southbridge_smi_tco(void) static void southbridge_smi_tco(void)
{ {
u32 tco_sts; u32 tco_sts;

1
src/southbridge/intel/common/spi.c
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@ -718,7 +718,6 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
return 0; return 0;
} }
static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset, static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset,
size_t len) size_t len)
{ {

1
src/southbridge/intel/i82371eb/smbus.c
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@ -92,7 +92,6 @@ static void pwrmgt_read_resources(struct device *dev)
IORESOURCE_RESERVE; IORESOURCE_RESERVE;
} }
static const struct smbus_bus_operations lops_smbus_bus = { static const struct smbus_bus_operations lops_smbus_bus = {
}; };

1
src/southbridge/intel/i82801dx/ac97.c
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@ -33,7 +33,6 @@
#define MBAR 0x14 #define MBAR 0x14
#define SEC_CODEC 0x40 #define SEC_CODEC 0x40
/* FIXME. This table is probably mainboard specific */ /* FIXME. This table is probably mainboard specific */
static u16 ac97_function[16*2][4] = { static u16 ac97_function[16*2][4] = {
{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) }, { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },

1
src/southbridge/intel/i82801dx/fadt.c
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@ -20,7 +20,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
{ {
u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe;
fadt->sci_int = 0x9; fadt->sci_int = 0x9;
if (permanent_smi_handler()) { if (permanent_smi_handler()) {

3
src/southbridge/intel/i82801dx/i82801dx.h
View File

@ -46,8 +46,6 @@ void aseg_smm_lock(void);
/* IDE_TIM bits */ /* IDE_TIM bits */
#define IDE_DECODE_ENABLE (1 << 15) #define IDE_DECODE_ENABLE (1 << 15)
#define PCI_DMA_CFG 0x90 #define PCI_DMA_CFG 0x90
#define SERIRQ_CNTL 0x64 #define SERIRQ_CNTL 0x64
#define GEN_CNTL 0xd0 #define GEN_CNTL 0xd0
@ -93,7 +91,6 @@ void aseg_smm_lock(void);
#define RTC_FAILED (1 <<2) #define RTC_FAILED (1 <<2)
#define PM1_STS 0x00 #define PM1_STS 0x00
#define WAK_STS (1 << 15) #define WAK_STS (1 << 15)
#define PCIEXPWAK_STS (1 << 14) #define PCIEXPWAK_STS (1 << 14)

9
src/southbridge/intel/i82801dx/smi.c
View File

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <console/console.h> #include <console/console.h>
@ -13,7 +12,6 @@
#include <string.h> #include <string.h>
#include "i82801dx.h" #include "i82801dx.h"
void northbridge_write_smram(u8 smram); void northbridge_write_smram(u8 smram);
/* For intel/e7505. */ /* For intel/e7505. */
@ -98,7 +96,6 @@ static void dump_smi_status(u32 smi_sts)
printk(BIOS_DEBUG, "\n"); printk(BIOS_DEBUG, "\n");
} }
/** /**
* @brief read and clear GPE0_STS * @brief read and clear GPE0_STS
* @return GPE0_STS register * @return GPE0_STS register
@ -138,7 +135,6 @@ static void dump_gpe0_status(u32 gpe0_sts)
printk(BIOS_DEBUG, "\n"); printk(BIOS_DEBUG, "\n");
} }
/** /**
* @brief read and clear ALT_GP_SMI_STS * @brief read and clear ALT_GP_SMI_STS
* @return ALT_GP_SMI_STS register * @return ALT_GP_SMI_STS register
@ -164,8 +160,6 @@ static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
printk(BIOS_DEBUG, "\n"); printk(BIOS_DEBUG, "\n");
} }
/** /**
* @brief read and clear TCOx_STS * @brief read and clear TCOx_STS
* @return TCOx_STS registers * @return TCOx_STS registers
@ -184,7 +178,6 @@ static u32 reset_tco_status(void)
return reg32; return reg32;
} }
static void dump_tco_status(u32 tco_sts) static void dump_tco_status(u32 tco_sts)
{ {
printk(BIOS_DEBUG, "TCO_STS: "); printk(BIOS_DEBUG, "TCO_STS: ");
@ -204,8 +197,6 @@ static void dump_tco_status(u32 tco_sts)
printk(BIOS_DEBUG, "\n"); printk(BIOS_DEBUG, "\n");
} }
/** /**
* @brief Set the EOS bit * @brief Set the EOS bit
*/ */

6
src/southbridge/intel/i82801dx/smihandler.c
View File

@ -96,7 +96,6 @@ static void dump_smi_status(u32 smi_sts)
printk(BIOS_DEBUG, "\n"); printk(BIOS_DEBUG, "\n");
} }
/** /**
* @brief read and clear GPE0_STS * @brief read and clear GPE0_STS
* @return GPE0_STS register * @return GPE0_STS register
@ -136,7 +135,6 @@ static void dump_gpe0_status(u32 gpe0_sts)
printk(BIOS_DEBUG, "\n"); printk(BIOS_DEBUG, "\n");
} }
/** /**
* @brief read and clear TCOx_STS * @brief read and clear TCOx_STS
* @return TCOx_STS registers * @return TCOx_STS registers
@ -155,7 +153,6 @@ static u32 reset_tco_status(void)
return reg32; return reg32;
} }
static void dump_tco_status(u32 tco_sts) static void dump_tco_status(u32 tco_sts)
{ {
printk(BIOS_DEBUG, "TCO_STS: "); printk(BIOS_DEBUG, "TCO_STS: ");
@ -222,7 +219,6 @@ static void busmaster_disable_on_bus(int bus)
} }
} }
static void southbridge_smi_sleep(void) static void southbridge_smi_sleep(void)
{ {
u8 reg8; u8 reg8;
@ -389,8 +385,6 @@ static void southbridge_smi_mc(void)
printk(BIOS_DEBUG, "Microcontroller SMI.\n"); printk(BIOS_DEBUG, "Microcontroller SMI.\n");
} }
static void southbridge_smi_tco(void) static void southbridge_smi_tco(void)
{ {
u32 tco_sts; u32 tco_sts;

1
src/southbridge/intel/i82801gx/ac97.c
View File

@ -34,7 +34,6 @@
#define MBAR 0x14 #define MBAR 0x14
#define SEC_CODEC 0x40 #define SEC_CODEC 0x40
/* FIXME. This table is probably mainboard specific */ /* FIXME. This table is probably mainboard specific */
static u16 ac97_function[16*2][4] = { static u16 ac97_function[16*2][4] = {
{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) }, { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },

1
src/southbridge/intel/i82801gx/lpc.c
View File

@ -411,7 +411,6 @@ unsigned long acpi_fill_madt(unsigned long current)
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL);
return current; return current;
} }

1
src/southbridge/intel/i82801gx/smbus.c
View File

@ -58,7 +58,6 @@ static int lsmbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buf)
return do_smbus_block_read(res->base, device, cmd, bytes, buf); return do_smbus_block_read(res->base, device, cmd, bytes, buf);
} }
static struct smbus_bus_operations lops_smbus_bus = { static struct smbus_bus_operations lops_smbus_bus = {
.read_byte = lsmbus_read_byte, .read_byte = lsmbus_read_byte,
.write_byte = lsmbus_write_byte, .write_byte = lsmbus_write_byte,

1
src/southbridge/intel/i82801gx/smihandler.c
View File

@ -58,7 +58,6 @@ void southbridge_smi_monitor(void)
mask |= (0xff << ((i - 16) << 2)); mask |= (0xff << ((i - 16) << 2));
} }
/* IOTRAP(3) SMI function call */ /* IOTRAP(3) SMI function call */
if (IOTRAP(3)) { if (IOTRAP(3)) {
if (gnvs && gnvs->smif) if (gnvs && gnvs->smif)

2
src/southbridge/intel/i82801ix/dmi_setup.c
View File

@ -38,7 +38,6 @@ void i82801ix_dmi_setup(void)
RCBA8(RCBA_BCR) = 0x45; RCBA8(RCBA_BCR) = 0x45;
RCBA32(RCBA_CIR6) &= ~(1 << 7); RCBA32(RCBA_CIR6) &= ~(1 << 7);
/* VC1 setup for isochronous transfers: */ /* VC1 setup for isochronous transfers: */
/* Set VC1 virtual channel id to 1. */ /* Set VC1 virtual channel id to 1. */
@ -60,7 +59,6 @@ void i82801ix_dmi_setup(void)
/* Enable VC1. */ /* Enable VC1. */
RCBA32(RCBA_V1CTL) |= (1 << 31); RCBA32(RCBA_V1CTL) |= (1 << 31);
/* Setup RCRB: */ /* Setup RCRB: */
/* Set component id to 2 for southbridge, northbridge has id 1. */ /* Set component id to 2 for southbridge, northbridge has id 1. */

8
src/southbridge/intel/i82801ix/i82801ix.h
View File

@ -20,11 +20,8 @@
#define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60) #define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60)
#define DEFAULT_GPIOBASE 0x00000580 #define DEFAULT_GPIOBASE 0x00000580
#define APM_CNT 0xb2 #define APM_CNT 0xb2
#define GP_IO_USE_SEL 0x00 #define GP_IO_USE_SEL 0x00
#define GP_IO_SEL 0x04 #define GP_IO_SEL 0x04
#define GP_LVL 0x0c #define GP_LVL 0x0c
@ -73,23 +70,19 @@
#define D31F0_CxSTATE_CNF 0xa9 #define D31F0_CxSTATE_CNF 0xa9
#define D31F0_C4TIMING_CNT 0xaa #define D31F0_C4TIMING_CNT 0xaa
/* D31:F2 SATA */ /* D31:F2 SATA */
#define D31F2_IDE_TIM_PRI 0x40 #define D31F2_IDE_TIM_PRI 0x40
#define D31F2_IDE_TIM_SEC 0x42 #define D31F2_IDE_TIM_SEC 0x42
#define D31F2_SIDX 0xa0 #define D31F2_SIDX 0xa0
#define D31F2_SDAT 0xa4 #define D31F2_SDAT 0xa4
/* D30:F0 PCI-to-PCI bridge */ /* D30:F0 PCI-to-PCI bridge */
#define D30F0_SMLT 0x1b #define D30F0_SMLT 0x1b
/* D28:F0-5 PCIe root ports */ /* D28:F0-5 PCIe root ports */
#define D28Fx_XCAP 0x42 #define D28Fx_XCAP 0x42
#define D28Fx_SLCAP 0x54 #define D28Fx_SLCAP 0x54
/* PCI Configuration Space (D31:F3): SMBus */ /* PCI Configuration Space (D31:F3): SMBus */
#define SMB_BASE 0x20 #define SMB_BASE 0x20
#define HOSTC 0x40 #define HOSTC 0x40
@ -154,7 +147,6 @@
#define FD_SD (1 << 3) /* SMBus */ #define FD_SD (1 << 3) /* SMBus */
#define FD_SAD1 (1 << 2) /* SATA #1 */ #define FD_SAD1 (1 << 2) /* SATA #1 */
#ifndef __ACPI__ #ifndef __ACPI__
#ifndef __ASSEMBLER__ #ifndef __ASSEMBLER__

1
src/southbridge/intel/i82801ix/smi.c
View File

@ -114,7 +114,6 @@ static void aseg_smm_install(void)
return; return;
smm_handler_copied = 1; smm_handler_copied = 1;
/* if we're resuming from S3, the SMM code is already in place, /* if we're resuming from S3, the SMM code is already in place,
* so don't copy it again to keep the current SMM state */ * so don't copy it again to keep the current SMM state */

1
src/southbridge/intel/i82801ix/smihandler.c
View File

@ -51,7 +51,6 @@ void southbridge_smi_monitor(void)
mask |= (0xff << ((i - 16) << 3)); mask |= (0xff << ((i - 16) << 3));
} }
/* IOTRAP(3) SMI function call */ /* IOTRAP(3) SMI function call */
if (IOTRAP(3)) { if (IOTRAP(3)) {
if (gnvs && gnvs->smif) if (gnvs && gnvs->smif)

8
src/southbridge/intel/i82801jx/i82801jx.h
View File

@ -11,11 +11,8 @@
#define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60) #define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60)
#define DEFAULT_GPIOBASE 0x00000580 #define DEFAULT_GPIOBASE 0x00000580
#define APM_CNT 0xb2 #define APM_CNT 0xb2
#define GP_IO_USE_SEL 0x00 #define GP_IO_USE_SEL 0x00
#define GP_IO_SEL 0x04 #define GP_IO_SEL 0x04
#define GP_LVL 0x0c #define GP_LVL 0x0c
@ -66,23 +63,19 @@
#define D31F0_C4TIMING_CNT 0xaa #define D31F0_C4TIMING_CNT 0xaa
#define D31F0_GPIO_ROUT 0xb8 #define D31F0_GPIO_ROUT 0xb8
/* D31:F2 SATA */ /* D31:F2 SATA */
#define D31F2_IDE_TIM_PRI 0x40 #define D31F2_IDE_TIM_PRI 0x40
#define D31F2_IDE_TIM_SEC 0x42 #define D31F2_IDE_TIM_SEC 0x42
#define D31F2_SIDX 0xa0 #define D31F2_SIDX 0xa0
#define D31F2_SDAT 0xa4 #define D31F2_SDAT 0xa4
/* D30:F0 PCI-to-PCI bridge */ /* D30:F0 PCI-to-PCI bridge */
#define D30F0_SMLT 0x1b #define D30F0_SMLT 0x1b
/* D28:F0-5 PCIe root ports */ /* D28:F0-5 PCIe root ports */
#define D28Fx_XCAP 0x42 #define D28Fx_XCAP 0x42
#define D28Fx_SLCAP 0x54 #define D28Fx_SLCAP 0x54
/* PCI Configuration Space (D31:F3): SMBus */ /* PCI Configuration Space (D31:F3): SMBus */
#define SMB_BASE 0x20 #define SMB_BASE 0x20
#define HOSTC 0x40 #define HOSTC 0x40
@ -164,7 +157,6 @@
#define FD_SD (1 << 3) /* SMBus */ #define FD_SD (1 << 3) /* SMBus */
#define FD_SAD1 (1 << 2) /* SATA #1 */ #define FD_SAD1 (1 << 2) /* SATA #1 */
#ifndef __ACPI__ #ifndef __ACPI__
#include <device/pci_ops.h> #include <device/pci_ops.h>

1
src/southbridge/intel/i82801jx/lpc.c
View File

@ -408,7 +408,6 @@ unsigned long acpi_fill_madt(unsigned long current)
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL);
return current; return current;
} }

1
src/southbridge/intel/i82801jx/smihandler.c
View File

@ -52,7 +52,6 @@ void southbridge_smi_monitor(void)
mask |= (0xff << ((i - 16) << 3)); mask |= (0xff << ((i - 16) << 3));
} }
/* IOTRAP(3) SMI function call */ /* IOTRAP(3) SMI function call */
if (IOTRAP(3)) { if (IOTRAP(3)) {
if (gnvs && gnvs->smif) if (gnvs && gnvs->smif)

1
src/southbridge/intel/ibexpeak/bootblock.c
View File

@ -74,7 +74,6 @@ static void early_lpc_init(void)
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
} }
void bootblock_early_southbridge_init(void) void bootblock_early_southbridge_init(void)
{ {
enable_spi_prefetching_and_caching(); enable_spi_prefetching_and_caching();

1
src/southbridge/intel/ibexpeak/fadt.c
View File

@ -13,7 +13,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
int c2_latency; int c2_latency;
fadt->sci_int = 0x9; fadt->sci_int = 0x9;
if (permanent_smi_handler()) { if (permanent_smi_handler()) {

1
src/southbridge/intel/ibexpeak/lpc.c
View File

@ -618,7 +618,6 @@ static struct device_operations device_ops = {
.ops_pci = &pci_dev_ops_pci, .ops_pci = &pci_dev_ops_pci,
}; };
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_IBEXPEAK_LPC_QM57, PCI_DID_INTEL_IBEXPEAK_LPC_QM57,
PCI_DID_INTEL_IBEXPEAK_LPC_HM55, PCI_DID_INTEL_IBEXPEAK_LPC_HM55,

1
src/southbridge/intel/ibexpeak/me.c
View File

@ -604,7 +604,6 @@ static const unsigned short pci_device_ids[] = {
0 0
}; };
static const struct pci_driver intel_me __pci_driver = { static const struct pci_driver intel_me __pci_driver = {
.ops = &device_ops, .ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VENDOR_ID_INTEL,

1
src/southbridge/intel/ibexpeak/me.h
View File

@ -198,7 +198,6 @@ struct me_fw_version {
u16 recovery_hot_fix; u16 recovery_hot_fix;
} __packed; } __packed;
#define HECI_EOP_STATUS_SUCCESS 0x0 #define HECI_EOP_STATUS_SUCCESS 0x0
#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1

1
src/southbridge/intel/ibexpeak/smihandler.c
View File

@ -107,7 +107,6 @@ void southbridge_smi_monitor(void)
mask |= (0xff << ((i - 16) << 2)); mask |= (0xff << ((i - 16) << 2));
} }
/* IOTRAP(3) SMI function call */ /* IOTRAP(3) SMI function call */
if (IOTRAP(3)) { if (IOTRAP(3)) {
if (gnvs && gnvs->smif) if (gnvs && gnvs->smif)

1
src/southbridge/intel/ibexpeak/usb_ehci.c
View File

@ -66,7 +66,6 @@ static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
pci_write_config8(dev, 0x80, access_cntl); pci_write_config8(dev, 0x80, access_cntl);
} }
static struct pci_operations lops_pci = { static struct pci_operations lops_pci = {
.set_subsystem = &usb_ehci_set_subsystem, .set_subsystem = &usb_ehci_set_subsystem,
}; };

1
src/southbridge/intel/lynxpoint/chip.h
View File

@ -91,5 +91,4 @@ struct southbridge_intel_lynxpoint_config {
bool docking_supported; bool docking_supported;
}; };
#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */ #endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */

1
src/southbridge/intel/lynxpoint/lp_gpio.c
View File

@ -19,7 +19,6 @@ static u16 get_gpio_base(void)
#endif #endif
} }
/* /*
* This function will return a number that indicates which PIRQ * This function will return a number that indicates which PIRQ
* this GPIO maps to. If this is not a PIRQ capable GPIO then * this GPIO maps to. If this is not a PIRQ capable GPIO then

1
src/southbridge/intel/lynxpoint/lpc.c
View File

@ -791,7 +791,6 @@ static struct device_operations device_ops = {
.ops_pci = &pci_dev_ops_pci, .ops_pci = &pci_dev_ops_pci,
}; };
/* IDs for LPC device of Intel 8 Series Chipset (Lynx Point) */ /* IDs for LPC device of Intel 8 Series Chipset (Lynx Point) */
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
0x8c41, /* Mobile Full Featured Engineering Sample. */ 0x8c41, /* Mobile Full Featured Engineering Sample. */

6
src/southbridge/intel/lynxpoint/pmutil.c
View File

@ -57,7 +57,6 @@ static void print_gpio_status(u32 status, int start)
} }
} }
/* /*
* PM1_CNT * PM1_CNT
*/ */
@ -78,7 +77,6 @@ void disable_pm1_control(u32 mask)
outl(pm1_cnt, get_pmbase() + PM1_CNT); outl(pm1_cnt, get_pmbase() + PM1_CNT);
} }
/* /*
* PM1 * PM1
*/ */
@ -127,7 +125,6 @@ void enable_pm1(u16 events)
outw(events, get_pmbase() + PM1_EN); outw(events, get_pmbase() + PM1_EN);
} }
/* /*
* SMI * SMI
*/ */
@ -198,7 +195,6 @@ void disable_smi(u32 mask)
outl(smi_en, get_pmbase() + SMI_EN); outl(smi_en, get_pmbase() + SMI_EN);
} }
/* /*
* ALT_GP_SMI * ALT_GP_SMI
*/ */
@ -298,7 +294,6 @@ void enable_alt_smi(u32 mask)
} }
} }
/* /*
* TCO * TCO
*/ */
@ -368,7 +363,6 @@ void enable_tco_sci(void)
enable_gpe(TCOSCI_EN); enable_gpe(TCOSCI_EN);
} }
/* /*
* GPE0 * GPE0
*/ */

4
src/southbridge/intel/lynxpoint/smihandler.c
View File

@ -78,7 +78,6 @@ static void busmaster_disable_on_bus(int bus)
} }
} }
static void southbridge_smi_sleep(void) static void southbridge_smi_sleep(void)
{ {
u8 reg8; u8 reg8;
@ -379,8 +378,6 @@ static void southbridge_smi_mc(void)
printk(BIOS_DEBUG, "Microcontroller SMI.\n"); printk(BIOS_DEBUG, "Microcontroller SMI.\n");
} }
static void southbridge_smi_tco(void) static void southbridge_smi_tco(void)
{ {
u32 tco_sts = clear_tco_status(); u32 tco_sts = clear_tco_status();
@ -443,7 +440,6 @@ static void southbridge_smi_monitor(void)
mask |= (0xff << ((i - 16) << 2)); mask |= (0xff << ((i - 16) << 2));
} }
/* IOTRAP(3) SMI function call */ /* IOTRAP(3) SMI function call */
if (IOTRAP(3)) { if (IOTRAP(3)) {
if (gnvs && gnvs->smif) if (gnvs && gnvs->smif)

3
src/southbridge/ricoh/rl5c476/rl5c476.c
View File

@ -107,11 +107,9 @@ static void rl5c476_init(struct device *dev)
pc16->moffl0 = 0; pc16->moffl0 = 0;
pc16->moffh0 = 0x40; pc16->moffh0 = 0x40;
/* set I/O width for Auto Data width */ /* set I/O width for Auto Data width */
pc16->ioctrl = 0x22; pc16->ioctrl = 0x22;
/* enable I/O window 0 and 1 */ /* enable I/O window 0 and 1 */
pc16->awinen = 0xc1; pc16->awinen = 0xc1;
@ -125,7 +123,6 @@ static void rl5c476_init(struct device *dev)
pc16->igctrl = 0x69; pc16->igctrl = 0x69;
/* 16 bit CF always have first config byte at 0x200 into /* 16 bit CF always have first config byte at 0x200 into
* Config structure, but CF+ may not according to spec - * Config structure, but CF+ may not according to spec -
* should locate through reading tuple data, but this should * should locate through reading tuple data, but this should

2
src/southbridge/ricoh/rl5c476/rl5c476.h
View File

@ -2,10 +2,8 @@
/* rl5c476 routines and defines*/ /* rl5c476 routines and defines*/
#include <stdint.h> #include <stdint.h>
/* the 16 bit control structure for ricoh cardbus bridge */ /* the 16 bit control structure for ricoh cardbus bridge */
typedef struct pc16reg { typedef struct pc16reg {
u8 idrevs; u8 idrevs;