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mb/google/zork/var/shuboz: Decrease I2C3 CLK below 400 kHz 

Modify I2C3 setting to follow I2C specification (lower than 400kHz).
Original setting:
.rise_time_ns = 184
.fall_time_ns = 42

Change to:
.rise_time_ns = 110
.fall_time_ns = 34

BUG=b:181091107
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ibdbb9a7dde524bdbde4789ee7ea005646080d97a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Kane Chen 2021-02-24 17:45:07 +08:00 committed by Patrick Georgi
parent d992944d09
commit 13818f5c5c
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/google/zork/variants/shuboz/overridetree.cb
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@ -35,8 +35,8 @@ chip soc/amd/picasso
register "i2c[3]" = "{ register "i2c[3]" = "{
.speed = I2C_SPEED_FAST, .speed = I2C_SPEED_FAST,
.rise_time_ns = 184, /* 0 to 1.26v (1.8 * .7) */ .rise_time_ns = 110, /* 0 to 1.26v (1.8 * .7) */
.fall_time_ns = 42, /* 1.26v to 0 */ .fall_time_ns = 34, /* 1.26v to 0 */
.early_init = true, .early_init = true,
}" }"