amd/geode_lx: Fix .c includes
Change-Id: I2cce52561d30e30e1c81752cd2a455e7211006eb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
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64aa881263
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@ -3,6 +3,10 @@ subdirs-y += ../../x86/lapic
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subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/smm
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subdirs-y += ../../x86/smm
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romstage-y += cpureginit.c
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romstage-y += syspreinit.c
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romstage-y += msrinit.c
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ramstage-y += geode_lx_init.c
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ramstage-y += geode_lx_init.c
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ramstage-y += cpubug.c
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ramstage-y += cpubug.c
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@ -16,9 +16,13 @@
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* GNU General Public License for more details.
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* GNU General Public License for more details.
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*/
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*/
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/* SetDelayControl */
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#include <stdint.h>
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#include "cpu/x86/msr.h"
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#include <spd.h>
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/lxdef.h>
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#include <northbridge/amd/lx/raminit.h>
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#include <northbridge/amd/lx/northbridge.h>
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/**
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/**
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* Delay Control Settings table from AMD (MCP 0x4C00000F).
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* Delay Control Settings table from AMD (MCP 0x4C00000F).
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@ -14,7 +14,9 @@
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*/
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*/
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#include <stdlib.h>
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#include <stdlib.h>
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#include "cpu/x86/msr.h"
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#include <cpu/amd/lxdef.h>
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#include <cpu/x86/msr.h>
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#include <northbridge/amd/lx/northbridge.h>
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static const msrinit_t msr_table[] =
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static const msrinit_t msr_table[] =
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{
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{
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@ -50,7 +52,7 @@ static const msrinit_t msr_table[] =
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{MSR_GLIU1_SYSMEM, {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000
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{MSR_GLIU1_SYSMEM, {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000
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};
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};
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static void msr_init(void)
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void lx_msr_init(void)
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{
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{
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int i;
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int i;
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for (i = 0; i < ARRAY_SIZE(msr_table); i++)
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for (i = 0; i < ARRAY_SIZE(msr_table); i++)
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@ -16,6 +16,9 @@
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* GNU General Public License for more details.
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* GNU General Public License for more details.
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*/
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*/
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#include <arch/io.h>
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#include <cpu/amd/lxdef.h>
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/**
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/**
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* StartTimer1
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* StartTimer1
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*
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*
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@ -644,6 +644,10 @@
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#define DELAY_LOWER_STATUS_MASK 0x7C0
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#define DELAY_LOWER_STATUS_MASK 0x7C0
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#if !defined(__ASSEMBLER__)
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#if !defined(__ASSEMBLER__)
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#include <stdint.h>
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#include <arch/cpu.h>
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#if defined(__PRE_RAM__)
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#if defined(__PRE_RAM__)
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void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated);
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void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated);
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void SystemPreInit(void);
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void SystemPreInit(void);
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@ -25,14 +25,14 @@
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#include <cpu/x86/msr.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/lxdef.h>
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#include <cpu/amd/lxdef.h>
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#include <cpu/amd/car.h>
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#include <cpu/amd/car.h>
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#include <southbridge/amd/cs5536/cs5536.h>
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#include <northbridge/amd/lx/raminit.h>
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#include <northbridge/amd/lx/raminit.h>
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#include <northbridge/amd/lx/northbridge.h>
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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#include <southbridge/amd/cs5536/cs5536.h>
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#include <superio/winbond/common/winbond.h>
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#include <superio/winbond/common/winbond.h>
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#include <superio/winbond/w83627hf/w83627hf.h>
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#include <superio/winbond/w83627hf/w83627hf.h>
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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/* The part is a Hynix hy5du121622ctp-d43.
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/* The part is a Hynix hy5du121622ctp-d43.
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*
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*
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* HY 5D U 12 16 2 2 C <blank> T <blank> P D43
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* HY 5D U 12 16 2 2 C <blank> T <blank> P D43
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@ -88,11 +88,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
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return spdbytes[address];
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return spdbytes[address];
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}
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}
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#include "northbridge/amd/lx/pll_reset.c"
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#include "cpu/amd/geode_lx/cpureginit.c"
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#include "cpu/amd/geode_lx/syspreinit.c"
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#include "cpu/amd/geode_lx/msrinit.c"
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void asmlinkage mainboard_romstage_entry(unsigned long bist)
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void asmlinkage mainboard_romstage_entry(unsigned long bist)
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{
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{
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static const struct mem_controller memctrl[] = {
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static const struct mem_controller memctrl[] = {
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@ -100,7 +95,7 @@ void asmlinkage mainboard_romstage_entry(unsigned long bist)
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};
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};
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SystemPreInit();
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SystemPreInit();
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msr_init();
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lx_msr_init();
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cs5536_early_setup();
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cs5536_early_setup();
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@ -114,7 +109,7 @@ void asmlinkage mainboard_romstage_entry(unsigned long bist)
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/* Halt if there was a built in self test failure */
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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report_bist_failure(bist);
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pll_reset();
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lx_pll_reset();
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cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
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cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
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@ -27,6 +27,7 @@
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#include <cpu/amd/car.h>
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#include <cpu/amd/car.h>
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#include <southbridge/amd/cs5536/cs5536.h>
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#include <southbridge/amd/cs5536/cs5536.h>
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#include <northbridge/amd/lx/raminit.h>
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#include <northbridge/amd/lx/raminit.h>
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#include <northbridge/amd/lx/northbridge.h>
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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@ -85,11 +86,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
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return spdbytes[address];
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return spdbytes[address];
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}
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}
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#include "northbridge/amd/lx/pll_reset.c"
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#include "cpu/amd/geode_lx/cpureginit.c"
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#include "cpu/amd/geode_lx/syspreinit.c"
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#include "cpu/amd/geode_lx/msrinit.c"
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/** Early mainboard specific GPIO setup. */
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/** Early mainboard specific GPIO setup. */
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static void mb_gpio_init(void)
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static void mb_gpio_init(void)
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{
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{
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@ -122,7 +118,7 @@ void asmlinkage mainboard_romstage_entry(unsigned long bist)
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};
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};
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SystemPreInit();
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SystemPreInit();
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msr_init();
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lx_msr_init();
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cs5536_early_setup();
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cs5536_early_setup();
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@ -136,7 +132,7 @@ void asmlinkage mainboard_romstage_entry(unsigned long bist)
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/* Halt if there was a built in self test failure */
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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report_bist_failure(bist);
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pll_reset();
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lx_pll_reset();
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cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
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cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
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@ -6,5 +6,6 @@ ramstage-y += grphinit.c
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romstage-y += raminit.c
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romstage-y += raminit.c
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romstage-y += generic_sdram.c
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romstage-y += generic_sdram.c
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romstage-y += pll_reset.c
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endif
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endif
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@ -16,8 +16,6 @@
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#ifndef NORTHBRIDGE_AMD_LX_H
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#ifndef NORTHBRIDGE_AMD_LX_H
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#define NORTHBRIDGE_AMD_LX_H
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#define NORTHBRIDGE_AMD_LX_H
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#include <cpu/amd/lxdef.h>
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/* northbridge.c */
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/* northbridge.c */
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int sizeram(void);
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int sizeram(void);
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@ -26,4 +24,8 @@ void northbridge_init_early(void);
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/* pll_reset.c */
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/* pll_reset.c */
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unsigned int GeodeLinkSpeed(void);
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unsigned int GeodeLinkSpeed(void);
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void lx_pll_reset(void);
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void lx_msr_init(void);
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#endif
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#endif
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@ -14,9 +14,12 @@
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* GNU General Public License for more details.
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* GNU General Public License for more details.
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*/
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*/
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/lxdef.h>
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#include "northbridge.h"
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#include "northbridge.h"
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static void pll_reset(void)
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void lx_pll_reset(void)
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{
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{
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msr_t msrGlcpSysRstpll;
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msr_t msrGlcpSysRstpll;
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