soc/intel/xeon_sp: Move codes to support new PCH
Different PCHs have different definitions for registers. Here create a lbg folder and move lbg specific codes to this folder so that we can add new PCH code under xeon_sp folder. * Create lbg folder and move lbg specific codes from pch.c to soc_pch.c under lbg folder. * Rename lewisburg_pch_gpio_defs.h to gpio_soc_defs.h and move to lbg folder. * Rename gpio.c to soc_gpio.c and move to lbg folder. * Move pcr_ids.h to lbg folder. * Move lbg specific codes from pmutil.c to soc_pmutil.c under lbg folder. * Create and revise makefile for files under lbg folder. TEST=Can boot into OS on OCP Delta Lake. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I06555ed6612c632ea2ce1938d81781cd9348017a Reviewed-on: https://review.coreboot.org/c/coreboot/+/70009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
parent
cfad59a516
commit
13c44457f1
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@ -7,7 +7,7 @@
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#include <soc/romstage.h>
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#include <string.h>
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#include <gpio.h>
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#include <soc/lewisburg_pch_gpio_defs.h>
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#include <soc/gpio_soc_defs.h>
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#include <skxsp_tp_iio.h>
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#include "ipmi.h"
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@ -2,13 +2,13 @@
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ifeq ($(CONFIG_XEON_SP_COMMON_BASE),y)
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subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx
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subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx
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subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx lbg
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subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx lbg
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bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c
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romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c memmap.c
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bootblock-y += bootblock.c spi.c lpc.c pch.c
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romstage-y += romstage.c reset.c util.c spi.c pmutil.c memmap.c
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romstage-y += ../../../cpu/intel/car/romstage.c
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ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c ramstage.c chip_common.c
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ramstage-y += uncore.c reset.c util.c lpc.c spi.c ramstage.c chip_common.c
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ramstage-y += memmap.c pch.c lockdown.c finalize.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c pmutil.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += nb_acpi.c acpi.c
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@ -14,6 +14,7 @@
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#include <soc/chip_common.h>
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#include <soc/cpu.h>
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#include <soc/pch.h>
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#include <soc/soc_pch.h>
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#include <soc/ramstage.h>
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#include <soc/p2sb.h>
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#include <soc/soc_util.h>
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@ -3,7 +3,7 @@
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#ifndef _SOC_GPIO_H_
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#define _SOC_GPIO_H_
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#include <soc/lewisburg_pch_gpio_defs.h>
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#include <soc/gpio_soc_defs.h>
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#include <intelblocks/gpio.h>
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/*
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@ -10,6 +10,5 @@ void pch_disable_devfn(struct device *dev);
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#endif
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void override_hpet_ioapic_bdf(void);
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void pch_lock_dmictl(void);
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#endif /* _SOC_PCH_H_ */
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@ -0,0 +1,7 @@
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## SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += soc_pch.c soc_gpio.c
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romstage-y += soc_pmutil.c soc_gpio.c
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ramstage-y += soc_pmutil.c soc_pch.c soc_gpio.c
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CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/lbg/include
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@ -0,0 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _SOC_SOC_PCH_H_
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#define _SOC_SOC_PCH_H_
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void pch_lock_dmictl(void);
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#endif /* _SOC_SOC_PCH_H_ */
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@ -0,0 +1,58 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/pci_ops.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/rtc.h>
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#include <intelblocks/p2sb.h>
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#include <soc/bootblock.h>
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#include <soc/soc_pch.h>
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#include <soc/pmc.h>
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#include <console/console.h>
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#define PCR_DMI_ACPIBA 0x27B4
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#define PCR_DMI_ACPIBDID 0x27B8
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#define PCR_DMI_DMICTL 0x2234
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#define PCR_DMI_DMICTL_SRLOCK (1 << 31)
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#define PCR_DMI_PMBASEA 0x27AC
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#define PCR_DMI_PMBASEC 0x27B0
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static void soc_config_acpibase(void)
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{
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uint32_t reg32;
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/* Disable ABASE in PMC Device first before changing Base Address */
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reg32 = pci_read_config32(PCH_DEV_PMC, ACTL);
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pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~ACPI_EN);
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/* Program ACPI Base */
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pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS);
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/* Enable ACPI in PMC */
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pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | ACPI_EN);
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uint32_t data = pci_read_config32(PCH_DEV_PMC, ABASE);
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printk(BIOS_INFO, "%s : pmbase = %x\n", __func__, (int)data);
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/*
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* Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0]
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* to [0x3F, PMC PCI Offset 40h bit[15:2], 1]
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*/
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reg32 = (0x3f << 18) | ACPI_BASE_ADDRESS | 1;
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pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32);
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pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8);
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}
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void bootblock_pch_init(void)
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{
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/*
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* Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT
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*/
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soc_config_acpibase();
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}
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void pch_lock_dmictl(void)
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{
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uint32_t reg32 = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
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pcr_write32(PID_DMI, PCR_DMI_DMICTL, reg32 | PCR_DMI_DMICTL_SRLOCK);
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}
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@ -0,0 +1,81 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Helper functions for dealing with power management registers
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* and the differences between PCH variants.
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*/
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#define __SIMPLE_DEVICE__
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#include <console/console.h>
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#include <device/pci.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/rtc.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/pmc.h>
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uint8_t *pmc_mmio_regs(void)
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{
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return (void *)(uintptr_t) pci_read_config32(PCH_DEV_PMC, PWRMBASE);
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}
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uintptr_t soc_read_pmc_base(void)
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{
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return (uintptr_t) (pmc_mmio_regs());
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}
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uint32_t *soc_pmc_etr_addr(void)
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{
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/*
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* The pointer returned must not be cached, because the address depends on the
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* MMCONF base address and the assigned PCI bus number, which both may change
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* during the boot process!
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*/
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return pci_mmio_config32_addr(PCH_DEVFN_PMC << 12, ETR);
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}
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int soc_get_rtc_failed(void)
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{
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uint32_t pmcon_b = pci_s_read_config32(PCH_DEV_PMC, GEN_PMCON_B);
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int rtc_fail = !!(pmcon_b & RTC_BATTERY_DEAD);
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if (rtc_fail)
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printk(BIOS_ERR, "%s: RTC battery dead or removed\n", __func__);
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return rtc_fail;
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}
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void soc_fill_power_state(struct chipset_power_state *ps)
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{
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uint8_t *pmc;
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ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A);
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ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B);
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pmc = pmc_mmio_regs();
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ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
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ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
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printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
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ps->gen_pmcon_a, ps->gen_pmcon_b);
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printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
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ps->gblrst_cause[0], ps->gblrst_cause[1]);
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}
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/*
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* Set which power state system will be after reapplying
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* the power (from G3 State)
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*/
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void pmc_soc_set_afterg3_en(const bool on)
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{
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uint8_t reg8;
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reg8 = pci_read_config8(PCH_DEV_PMC, GEN_PMCON_B);
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if (on)
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reg8 &= ~SLEEP_AFTER_POWER_FAIL;
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else
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reg8 |= SLEEP_AFTER_POWER_FAIL;
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pci_write_config8(PCH_DEV_PMC, GEN_PMCON_B, reg8);
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}
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@ -11,46 +11,6 @@
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#include <soc/pmc.h>
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#include <console/console.h>
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#define PCR_DMI_ACPIBA 0x27B4
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#define PCR_DMI_ACPIBDID 0x27B8
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#define PCR_DMI_DMICTL 0x2234
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#define PCR_DMI_DMICTL_SRLOCK (1 << 31)
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#define PCR_DMI_PMBASEA 0x27AC
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#define PCR_DMI_PMBASEC 0x27B0
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static void soc_config_acpibase(void)
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{
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uint32_t reg32;
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/* Disable ABASE in PMC Device first before changing Base Address */
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reg32 = pci_read_config32(PCH_DEV_PMC, ACTL);
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pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~ACPI_EN);
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/* Program ACPI Base */
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pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS);
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/* Enable ACPI in PMC */
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pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | ACPI_EN);
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uint32_t data = pci_read_config32(PCH_DEV_PMC, ABASE);
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printk(BIOS_INFO, "%s : pmbase = %x\n", __func__, (int)data);
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/*
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* Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0]
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* to [0x3F, PMC PCI Offset 40h bit[15:2], 1]
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*/
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reg32 = (0x3f << 18) | ACPI_BASE_ADDRESS | 1;
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pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32);
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pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8);
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}
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void bootblock_pch_init(void)
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{
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/*
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* Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT
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*/
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soc_config_acpibase();
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}
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void override_hpet_ioapic_bdf(void)
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{
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union p2sb_bdf ioapic_bdf = {
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p2sb_set_ioapic_bdf(ioapic_bdf);
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p2sb_set_hpet_bdf(hpet_bdf);
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}
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void pch_lock_dmictl(void)
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{
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uint32_t reg32 = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
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pcr_write32(PID_DMI, PCR_DMI_DMICTL, reg32 | PCR_DMI_DMICTL_SRLOCK);
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}
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return gpe_sts_bits;
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}
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uint8_t *pmc_mmio_regs(void)
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{
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return (void *)(uintptr_t)pci_read_config32(PCH_DEV_PMC, PWRMBASE);
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}
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uintptr_t soc_read_pmc_base(void)
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{
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return (uintptr_t)(pmc_mmio_regs());
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}
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uint32_t *soc_pmc_etr_addr(void)
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{
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/*
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* The pointer returned must not be cached, because the address depends on the
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* MMCONF base address and the assigned PCI bus number, which both may change
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* during the boot process!
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*/
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return pci_mmio_config32_addr(PCH_DEVFN_PMC << 12, ETR);
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}
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void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
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{
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/* No functionality for this yet */
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}
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int soc_get_rtc_failed(void)
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{
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uint32_t pmcon_b = pci_s_read_config32(PCH_DEV_PMC, GEN_PMCON_B);
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int rtc_fail = !!(pmcon_b & RTC_BATTERY_DEAD);
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if (rtc_fail)
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printk(BIOS_ERR, "%s: RTC battery dead or removed\n", __func__);
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return rtc_fail;
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}
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/* Return 0, 3, or 5 to indicate the previous sleep state. */
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int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
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{
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return prev_sleep_state;
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}
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void soc_fill_power_state(struct chipset_power_state *ps)
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{
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uint8_t *pmc;
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ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A);
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ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B);
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pmc = pmc_mmio_regs();
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ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
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ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
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printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
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ps->gen_pmcon_a, ps->gen_pmcon_b);
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printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
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ps->gblrst_cause[0], ps->gblrst_cause[1]);
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}
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/* STM Support */
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uint16_t get_pmbase(void)
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{
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return ACPI_BASE_ADDRESS;
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}
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/*
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* Set which power state system will be after reapplying
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* the power (from G3 State)
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*/
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void pmc_soc_set_afterg3_en(const bool on)
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{
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uint8_t reg8;
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reg8 = pci_read_config8(PCH_DEV_PMC, GEN_PMCON_B);
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if (on)
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reg8 &= ~SLEEP_AFTER_POWER_FAIL;
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else
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reg8 |= SLEEP_AFTER_POWER_FAIL;
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pci_write_config8(PCH_DEV_PMC, GEN_PMCON_B, reg8);
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}
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#include <soc/acpi.h>
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#include <soc/chip_common.h>
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#include <soc/pch.h>
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#include <soc/soc_pch.h>
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#include <soc/ramstage.h>
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#include <soc/soc_util.h>
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#include <soc/util.h>
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