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mb/google/hatch: Disable GPIO community dynamic clock gating 

The dynamic clock gating is causing boards to miss interrupts
whose pulses are shorter than 4us.  Disable it using FSP UPDs.

BUG=b:130764684
BRANCH=none
TEST=Compiles

Change-Id: I8f1ec8f7c31192bce2a761ec99b86638435dc27c
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Tim Wawrzynczak 2019-07-09 13:33:04 -06:00 committed by Martin Roth
parent 20cfc87ca0
commit 145748bf25
1 changed files with 6 additions and 6 deletions
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12
src/mainboard/google/hatch/variants/baseboard/devicetree.cb
View File

@ -95,12 +95,12 @@ chip soc/intel/cannonlake
register "gpio_override_pm" = "1" register "gpio_override_pm" = "1"
# GPIO community PM configuration # GPIO community PM configuration
register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" # Disable dynamic clock gating; with bits 0-5 set in these registers,
register "gpio_pm[COMM_1]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" # some short interrupt pulses were missed (esp. cr50 irq)
register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" register "gpio_pm[COMM_0]" = "0"
register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" register "gpio_pm[COMM_1]" = "0"
# Disable clock gating on this community so that cr50's short irq register "gpio_pm[COMM_2]" = "0"
# pulses won't be missed. register "gpio_pm[COMM_3]" = "0"
register "gpio_pm[COMM_4]" = "0" register "gpio_pm[COMM_4]" = "0"
device cpu_cluster 0 on device cpu_cluster 0 on