soc/intel/elkhartlake: Correct I2C base clock to 100 MHz

According to measurements Elkhart Lake seems to drive the internal I2C
controllers with 100 MHz instead of the common 133 MHz. The datasheet
itself is quite vague on this definition, just one place mentions that
it is 100 MHz (register description for offset 0x94).

This patch changes the I2C controller base frequency to 100 MHz. The
verification was done by measuring the set up resulting I2C clock for
both 100 and 400 kHz.

Change-Id: I7c826bbb01b53e3661746e49f25441565068d1c2
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Werner Zeh 2022-11-07 07:50:51 +01:00 committed by Felix Held
parent 6b4a1ab82a
commit 14612f698c
1 changed files with 1 additions and 1 deletions

View File

@ -151,7 +151,7 @@ config CPU_XTAL_HZ
config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
int int
default 133 default 100
config SOC_INTEL_COMMON_BLOCK_GSPI_MAX config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
int int