arm64: No need of invalidating cache line for secondary CPU stack
With support for initializing registers based on values saved by primary CPU, we no longer need to invalidate secondary CPU stack cache lines. Before jumping to C environment, we enable caching and update the required registers. BUG=chrome-os-partner:33962 BRANCH=None TEST=Compiles and boots both CPU0 and CPU1 on ryu. Change-Id: Ifee36302b5de25b909b4570a30ada8ecd742ab82 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0a0403d06b89dae30b7520747501b0521d16a6db Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I738250f948e912725264cba3e389602af7510e3e Original-Reviewed-on: https://chromium-review.googlesource.com/231563 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9541 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -151,13 +151,6 @@ static void init_cpu_info(struct bus *bus)
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}
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}
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}
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}
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static void invalidate_cpu_stack_top(unsigned int id)
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{
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const size_t size = 128;
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char *stack = cpu_get_stack(id);
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dcache_invalidate_by_mva(stack - size, size);
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}
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void arch_initialize_cpus(device_t cluster, struct cpu_control_ops *cntrl_ops)
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void arch_initialize_cpus(device_t cluster, struct cpu_control_ops *cntrl_ops)
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{
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{
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size_t max_cpus;
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size_t max_cpus;
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@ -221,9 +214,6 @@ void arch_initialize_cpus(device_t cluster, struct cpu_control_ops *cntrl_ops)
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/* Start the CPU. */
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/* Start the CPU. */
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printk(BIOS_DEBUG, "Starting CPU%x\n", ci->id);
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printk(BIOS_DEBUG, "Starting CPU%x\n", ci->id);
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/* Ensure CPU's top of stack is not in the cache. */
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invalidate_cpu_stack_top(ci->id);
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if (cntrl_ops->start_cpu(ci->id, entry)) {
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if (cntrl_ops->start_cpu(ci->id, entry)) {
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printk(BIOS_ERR,
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printk(BIOS_ERR,
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"Failed to start CPU%x\n", ci->id);
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"Failed to start CPU%x\n", ci->id);
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