mb/google/brya/var/agah: Update ASPM settings for dGPU
After some debugging, it has been determined that the ASPM L0s substate is functional, but there is still some problem with ASPM L1 substates, so this patch updates ASPM status for the dGPU from disabled to L0s only. BUG=b:240390998 TEST=tested with nvidia tools Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I584bdbf26eda20246034263446492bf4daf5f3b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
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@ -80,7 +80,7 @@ chip soc/intel/alderlake
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.clk_req = 0,
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.clk_src = 0,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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.pcie_rp_aspm = ASPM_DISABLE
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.pcie_rp_aspm = ASPM_L0S,
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}"
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device pci 00.0 alias dgpu on end
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end
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@ -132,10 +132,6 @@ static void dgpu_power_sequence_on(void)
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void variant_init(void)
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{
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/* Disable ASPM for the GPU until it is verified working. */
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struct device *dgpu = DEV_PTR(dgpu);
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dgpu->disable_pcie_aspm = 1;
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if (acpi_is_wakeup_s3())
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return;
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