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soc/amd/cezanne,picasso: add AOAC offset define for the eMMC controller 

BUG=b:184978118

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I03554a151aa6a6d9e15d74c63cd02239b788808a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2021-06-15 16:01:44 +02:00
parent 17c89018a5
commit 1532d1c407
2 changed files with 2 additions and 0 deletions
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1
src/soc/amd/cezanne/include/soc/southbridge.h
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@ -117,6 +117,7 @@
#define FCH_AOAC_DEV_UART1 12 #define FCH_AOAC_DEV_UART1 12
#define FCH_AOAC_DEV_AMBA 17 #define FCH_AOAC_DEV_AMBA 17
#define FCH_AOAC_DEV_ESPI 27 #define FCH_AOAC_DEV_ESPI 27
#define FCH_AOAC_DEV_EMMC 28
void fch_pre_init(void); void fch_pre_init(void);
void fch_early_init(void); void fch_early_init(void);

1
src/soc/amd/picasso/include/soc/southbridge.h
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@ -130,6 +130,7 @@
#define FCH_AOAC_DEV_AMBA 17 #define FCH_AOAC_DEV_AMBA 17
#define FCH_AOAC_DEV_UART3 26 #define FCH_AOAC_DEV_UART3 26
#define FCH_AOAC_DEV_ESPI 27 #define FCH_AOAC_DEV_ESPI 27
#define FCH_AOAC_DEV_EMMC 28
#define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */