post_code: add post code for hardware initialization failure
Add a new post code POST_HW_INIT_FAILURE, used when coreboot fails to detect or initialize a required hardware component. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: I73820d24b3e1c269d9d446a78ef4f97e167e3552 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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@ -20,6 +20,7 @@ This is an (incomplete) list of POST codes emitted by coreboot v4.
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0xe1 Resource stored within CBFS is corrupt
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0xe2 Vendor binary (e.g. FSP) generated a fatal error
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0xe3 RAM could not be initialized
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0xe4 Critical hardware component could not initialize
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0xf8 Entry into elf boot
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0xf3 Jumping to payload
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@ -9,6 +9,7 @@ endif
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smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c
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smm-$(CONFIG_SMM_TSEG) += die.c
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smm-$(CONFIG_SMM_TSEG) += post.c
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verstage-y += init.c
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verstage-y += printk.c
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@ -348,6 +348,13 @@
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*/
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#define POST_RAM_FAILURE 0xe3
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/**
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* \brief Hardware initialization failure
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*
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* Set when a required hardware component was not found or is unsupported.
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*/
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#define POST_HW_INIT_FAILURE 0xe4
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/**
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* \brief TPM failure
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*
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@ -40,7 +40,8 @@ void *cbmem_top(void)
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config = dev->chip_info;
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if (!config)
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die("Failed to get chip_info\n");
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die_with_post_code(POST_HW_INIT_FAILURE,
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"Failed to get chip_info\n");
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/* FSP allocates 2x PRMRR Size Memory for alignment */
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if (config->sgx_enable)
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@ -120,7 +120,8 @@ static void soc_config_acpibase(void)
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pmc_base_reg = get_pmc_reg_base();
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if (!pmc_base_reg)
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die("Invalid PMC base address\n");
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die_with_post_code(POST_HW_INIT_FAILURE,
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"Invalid PMC base address\n");
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pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg +
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PCR_PSFX_TO_SHDW_BAR4);
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@ -221,7 +221,8 @@ static uintptr_t calculate_dram_base(size_t *reserved_mem_size)
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dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0));
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if (!dev)
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die("ERROR - IGD device not found!");
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die_with_post_code(POST_HW_INIT_FAILURE,
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"ERROR - IGD device not found!");
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/* Read TOLUD from Host Bridge offset */
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dram_base = sa_get_tolud_base();
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@ -58,7 +58,8 @@ uintptr_t graphics_get_memory_base(void)
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*/
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uintptr_t memory_base = graphics_get_bar(PCI_BASE_ADDRESS_2);
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if (!memory_base)
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die("GMADR is not programmed!");
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die_with_post_code(POST_HW_INIT_FAILURE,
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"GMADR is not programmed!");
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return memory_base;
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}
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@ -74,7 +75,8 @@ static uintptr_t graphics_get_gtt_base(void)
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if (!gtt_base) {
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gtt_base = graphics_get_bar(PCI_BASE_ADDRESS_0);
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if (!gtt_base)
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die("GTTMMADR is not programmed!");
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die_with_post_code(POST_HW_INIT_FAILURE,
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"GTTMMADR is not programmed!");
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}
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return gtt_base;
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}
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@ -36,7 +36,8 @@ static pci_devfn_t p2sb_get_device(void)
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pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn));
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if (dev == PCI_DEV_INVALID)
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die("PCH_DEV_P2SB not found!\n");
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die_with_post_code(POST_HW_INIT_FAILURE,
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"PCH_DEV_P2SB not found!\n");
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return dev;
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}
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@ -45,7 +46,8 @@ static struct device *p2sb_get_device(void)
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{
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struct device *dev = PCH_DEV_P2SB;
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if (!dev)
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die("PCH_DEV_P2SB not found!\n");
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die_with_post_code(POST_HW_INIT_FAILURE,
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"PCH_DEV_P2SB not found!\n");
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return dev;
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}
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@ -99,7 +101,8 @@ void p2sb_unhide(void)
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if (pci_read_config16(P2SB_GET_DEV, PCI_VENDOR_ID) !=
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PCI_VENDOR_ID_INTEL)
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die("Unable to unhide PCH_DEV_P2SB device !\n");
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die_with_post_code(POST_HW_INIT_FAILURE,
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"Unable to unhide PCH_DEV_P2SB device !\n");
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}
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void p2sb_hide(void)
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@ -108,7 +111,8 @@ void p2sb_hide(void)
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if (pci_read_config16(P2SB_GET_DEV, PCI_VENDOR_ID) !=
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0xFFFF)
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die("Unable to hide PCH_DEV_P2SB device !\n");
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die_with_post_code(POST_HW_INIT_FAILURE,
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"Unable to hide PCH_DEV_P2SB device !\n");
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}
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static void p2sb_configure_endpoints(int epmask_id, uint32_t mask)
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@ -91,7 +91,8 @@ static void pch_pmc_read_resources(struct device *dev)
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struct pmc_resource_config *config = &pmc_cfg;
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if (pmc_soc_get_resources(config) < 0)
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die("Unable to get PMC controller resource information!");
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die_with_post_code(POST_HW_INIT_FAILURE,
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"Unable to get PMC controller resource information!");
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/* Get the normal PCI resources of this device. */
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pci_dev_read_resources(dev);
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@ -98,7 +98,7 @@ static void sc_enable_ioapic(struct device *dev)
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reg32 = *ioapic_data;
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printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
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if (reg32 != (1 << 25))
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die("APIC Error\n");
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die_with_post_code(POST_HW_INIT_FAILURE, "APIC Error\n");
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printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
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for (i=0; i<3; i++) {
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@ -220,7 +220,8 @@ static uintptr_t calculate_dram_base(size_t *reserved_mem_size)
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dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0));
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if (!dev)
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die("ERROR - IGD device not found!");
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die_with_post_code(POST_HW_INIT_FAILURE,
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"ERROR - IGD device not found!");
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/* Read TOLUD from Host Bridge offset */
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dram_base = sa_get_tolud_base();
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@ -38,7 +38,8 @@ static void i2c_disable(I2C_REGS *regs)
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while (status & IC_ENABLE_CONTROLLER) {
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udelay(1);
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if (--timeout == 0)
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die("ERROR - I2C failed to disable!\n");
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die_with_post_code(POST_HW_INIT_FAILURE,
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"ERROR - I2C failed to disable!\n");
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status = regs->ic_enable_status;
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}
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