post_code: add post code for hardware initialization failure

Add a new post code POST_HW_INIT_FAILURE, used when coreboot fails to
detect or initialize a required hardware component.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms

Change-Id: I73820d24b3e1c269d9d446a78ef4f97e167e3552
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Keith Short 2019-05-09 11:40:34 -06:00 committed by Duncan Laurie
parent 24302633a5
commit 15588b03b3
12 changed files with 34 additions and 13 deletions

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@ -20,6 +20,7 @@ This is an (incomplete) list of POST codes emitted by coreboot v4.
0xe1 Resource stored within CBFS is corrupt
0xe2 Vendor binary (e.g. FSP) generated a fatal error
0xe3 RAM could not be initialized
0xe4 Critical hardware component could not initialize
0xf8 Entry into elf boot
0xf3 Jumping to payload

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@ -9,6 +9,7 @@ endif
smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c
smm-$(CONFIG_SMM_TSEG) += die.c
smm-$(CONFIG_SMM_TSEG) += post.c
verstage-y += init.c
verstage-y += printk.c

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@ -348,6 +348,13 @@
*/
#define POST_RAM_FAILURE 0xe3
/**
* \brief Hardware initialization failure
*
* Set when a required hardware component was not found or is unsupported.
*/
#define POST_HW_INIT_FAILURE 0xe4
/**
* \brief TPM failure
*

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@ -40,7 +40,8 @@ void *cbmem_top(void)
config = dev->chip_info;
if (!config)
die("Failed to get chip_info\n");
die_with_post_code(POST_HW_INIT_FAILURE,
"Failed to get chip_info\n");
/* FSP allocates 2x PRMRR Size Memory for alignment */
if (config->sgx_enable)

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@ -120,7 +120,8 @@ static void soc_config_acpibase(void)
pmc_base_reg = get_pmc_reg_base();
if (!pmc_base_reg)
die("Invalid PMC base address\n");
die_with_post_code(POST_HW_INIT_FAILURE,
"Invalid PMC base address\n");
pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg +
PCR_PSFX_TO_SHDW_BAR4);

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@ -221,7 +221,8 @@ static uintptr_t calculate_dram_base(size_t *reserved_mem_size)
dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0));
if (!dev)
die("ERROR - IGD device not found!");
die_with_post_code(POST_HW_INIT_FAILURE,
"ERROR - IGD device not found!");
/* Read TOLUD from Host Bridge offset */
dram_base = sa_get_tolud_base();

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@ -58,7 +58,8 @@ uintptr_t graphics_get_memory_base(void)
*/
uintptr_t memory_base = graphics_get_bar(PCI_BASE_ADDRESS_2);
if (!memory_base)
die("GMADR is not programmed!");
die_with_post_code(POST_HW_INIT_FAILURE,
"GMADR is not programmed!");
return memory_base;
}
@ -74,7 +75,8 @@ static uintptr_t graphics_get_gtt_base(void)
if (!gtt_base) {
gtt_base = graphics_get_bar(PCI_BASE_ADDRESS_0);
if (!gtt_base)
die("GTTMMADR is not programmed!");
die_with_post_code(POST_HW_INIT_FAILURE,
"GTTMMADR is not programmed!");
}
return gtt_base;
}

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@ -36,7 +36,8 @@ static pci_devfn_t p2sb_get_device(void)
pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn));
if (dev == PCI_DEV_INVALID)
die("PCH_DEV_P2SB not found!\n");
die_with_post_code(POST_HW_INIT_FAILURE,
"PCH_DEV_P2SB not found!\n");
return dev;
}
@ -45,7 +46,8 @@ static struct device *p2sb_get_device(void)
{
struct device *dev = PCH_DEV_P2SB;
if (!dev)
die("PCH_DEV_P2SB not found!\n");
die_with_post_code(POST_HW_INIT_FAILURE,
"PCH_DEV_P2SB not found!\n");
return dev;
}
@ -99,7 +101,8 @@ void p2sb_unhide(void)
if (pci_read_config16(P2SB_GET_DEV, PCI_VENDOR_ID) !=
PCI_VENDOR_ID_INTEL)
die("Unable to unhide PCH_DEV_P2SB device !\n");
die_with_post_code(POST_HW_INIT_FAILURE,
"Unable to unhide PCH_DEV_P2SB device !\n");
}
void p2sb_hide(void)
@ -108,7 +111,8 @@ void p2sb_hide(void)
if (pci_read_config16(P2SB_GET_DEV, PCI_VENDOR_ID) !=
0xFFFF)
die("Unable to hide PCH_DEV_P2SB device !\n");
die_with_post_code(POST_HW_INIT_FAILURE,
"Unable to hide PCH_DEV_P2SB device !\n");
}
static void p2sb_configure_endpoints(int epmask_id, uint32_t mask)

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@ -91,7 +91,8 @@ static void pch_pmc_read_resources(struct device *dev)
struct pmc_resource_config *config = &pmc_cfg;
if (pmc_soc_get_resources(config) < 0)
die("Unable to get PMC controller resource information!");
die_with_post_code(POST_HW_INIT_FAILURE,
"Unable to get PMC controller resource information!");
/* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev);

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@ -98,7 +98,7 @@ static void sc_enable_ioapic(struct device *dev)
reg32 = *ioapic_data;
printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
if (reg32 != (1 << 25))
die("APIC Error\n");
die_with_post_code(POST_HW_INIT_FAILURE, "APIC Error\n");
printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
for (i=0; i<3; i++) {

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@ -220,7 +220,8 @@ static uintptr_t calculate_dram_base(size_t *reserved_mem_size)
dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0));
if (!dev)
die("ERROR - IGD device not found!");
die_with_post_code(POST_HW_INIT_FAILURE,
"ERROR - IGD device not found!");
/* Read TOLUD from Host Bridge offset */
dram_base = sa_get_tolud_base();

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@ -38,7 +38,8 @@ static void i2c_disable(I2C_REGS *regs)
while (status & IC_ENABLE_CONTROLLER) {
udelay(1);
if (--timeout == 0)
die("ERROR - I2C failed to disable!\n");
die_with_post_code(POST_HW_INIT_FAILURE,
"ERROR - I2C failed to disable!\n");
status = regs->ic_enable_status;
}