GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/guybrush: Temporary fix to set eSPI mux 

This change allows guybrush EC communication while other patches
in the SOC code are worked on.

BUG=b:183149183
TEST=Boot guybrush with EC comunication

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I56fb64d4c065cf0665025346218cc66d77dacb52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51665
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mathew King 2021-03-19 11:39:14 -06:00 committed by Martin Roth
parent 39ef890336
commit 156be2db5a
1 changed files with 22 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
src/mainboard/google/guybrush/bootblock.c
View File

@ -1,14 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/acpimmio.h>
#include <bootblock_common.h>
#include <baseboard/variants.h>
#include <console/console.h>
#include <device/pci_ops.h>
#include <delay.h>
#include <gpio.h>
#include <soc/gpio.h>
#include <soc/pci_devs.h>
void bootblock_mainboard_early_init(void)
{
size_t num_gpios;
uint32_t dword;
const struct soc_amd_gpio *gpios;
if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) {
@ -16,6 +21,23 @@ void bootblock_mainboard_early_init(void)
program_gpios(gpios, num_gpios);
}
printk(BIOS_DEBUG, "Bootblock configure eSPI\n");
dword = pci_read_config32(SOC_LPC_DEV, 0x78);
dword &= 0xFFFFF9F3;
dword |= 0x200;
pci_write_config32(SOC_LPC_DEV, 0x78, dword);
pci_write_config32(SOC_LPC_DEV, 0x44, 0);
pci_write_config32(SOC_LPC_DEV, 0x48, 0);
dword = pm_read32(0x90);
dword |= 1 << 16;
pm_write32(0x90, dword);
dword = pm_read32(0x74);
dword |= 3 << 10;
pm_write32(0x74, dword);
if (CONFIG(GPIO_SIGN_OF_LIFE)) {
for (int x = 0; x < 20; x++) {
gpio_set(GPIO_31, 1);