commonlib: Add new "CSME ROM started execution" TS
BUG=b:182575295 TEST=Boot to OS, check cbmem -t 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 80,408 945:CSE started to handle ICC configuration 80,408 (0) 946:CSE sent 'Host BIOS Prep Done' to PMC 82,408 (2,000) 947:CSE received 'CPU Reset Done Ack sent' from PMC 242,408 (160,000) 0:1st timestamp 331,797 (89,389) 11:start of bootblock 359,484 (27,686) 12:end of bootblock 377,417 (17,932) Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I9e4ccd0b8c301e4eec1a09ee8919a577ade938ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/61168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -122,7 +122,7 @@ enum timestamp_id {
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TS_START_CSE_FW_SYNC = 948,
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TS_END_CSE_FW_SYNC = 949,
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/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
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/* 950+ reserved for vendorcode extensions (950-989: intel/fsp) */
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TS_FSP_MEMORY_INIT_START = 950,
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TS_FSP_MEMORY_INIT_END = 951,
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TS_FSP_TEMP_RAM_EXIT_START = 952,
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@ -140,6 +140,9 @@ enum timestamp_id {
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TS_FSP_MEMORY_INIT_LOAD = 970,
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TS_FSP_SILICON_INIT_LOAD = 971,
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/* 990+ reserved for vendorcode extensions (990-999: Intel ME continued) */
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TS_ME_ROM_START = 990,
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/* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
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/* Depthcharge entry IDs start at 1000 */
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@ -283,6 +286,7 @@ static const struct timestamp_id_to_name {
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{ TS_ME_RECEIVED_CRDA_FROM_PMC, "CSE received 'CPU Reset Done Ack sent' from PMC"},
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{ TS_START_CSE_FW_SYNC, "starting CSE firmware sync"},
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{ TS_END_CSE_FW_SYNC, "finished CSE firmware sync"},
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{ TS_ME_ROM_START, "CSME ROM started execution"},
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/* FSP related timestamps */
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{ TS_FSP_MEMORY_INIT_START, "calling FspMemoryInit" },
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