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mb/google/brya/var/felwinter: Use ACPI _PLD macro 

This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I33e4501fd689d642682891c7f5bc9cb7ca5e331c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61824
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2022-02-10 20:11:43 +05:30 committed by Felix Held
parent d2133c2ebf
commit 159db81b64
1 changed files with 6 additions and 36 deletions
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42
src/mainboard/google/brya/variants/felwinter/overridetree.cb
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@ -328,24 +328,14 @@ chip soc/intel/alderlake
register "desc" = ""USB3 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "{
.visible = true,
.panel = PLD_PANEL_RIGHT,
.horizontal_position = PLD_HORIZONTAL_POSITION_LEFT,
.shape = PLD_SHAPE_OVAL,
.group = ACPI_PLD_GROUP(1, 1)}"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
device ref tcss_usb3_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C2 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "{
.visible = true,
.panel = PLD_PANEL_LEFT,
.horizontal_position = PLD_HORIZONTAL_POSITION_LEFT,
.shape = PLD_SHAPE_OVAL,
.group = ACPI_PLD_GROUP(2, 1)}"
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
device ref tcss_usb3_port3 on end
end
end
@ -358,24 +348,14 @@ chip soc/intel/alderlake
register "desc" = ""USB2 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "{
.visible = true,
.panel = PLD_PANEL_RIGHT,
.horizontal_position = PLD_HORIZONTAL_POSITION_LEFT,
.shape = PLD_SHAPE_OVAL,
.group = ACPI_PLD_GROUP(1, 1)}"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
device ref usb2_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C2 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "{
.visible = true,
.panel = PLD_PANEL_LEFT,
.horizontal_position = PLD_HORIZONTAL_POSITION_LEFT,
.shape = PLD_SHAPE_OVAL,
.group = ACPI_PLD_GROUP(2, 1)}"
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
device ref usb2_port3 on end
end
chip drivers/usb/acpi
@ -387,12 +367,7 @@ chip soc/intel/alderlake
register "desc" = ""USB2 Type-A Port A0 (DB)""
register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
register "custom_pld" = "{
.visible = true,
.panel = PLD_PANEL_RIGHT,
.horizontal_position = PLD_HORIZONTAL_POSITION_LEFT,
.shape = PLD_SHAPE_HORIZONTAL_RECTANGLE,
.group = ACPI_PLD_GROUP(1, 2)}"
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
device ref usb2_port9 on end
end
chip drivers/usb/acpi
@ -406,12 +381,7 @@ chip soc/intel/alderlake
register "desc" = ""USB3 Type-A Port A0 (DB)""
register "type" = "UPC_TYPE_USB3_A"
register "use_custom_pld" = "true"
register "custom_pld" = "{
.visible = true,
.panel = PLD_PANEL_RIGHT,
.horizontal_position = PLD_HORIZONTAL_POSITION_LEFT,
.shape = PLD_SHAPE_HORIZONTAL_RECTANGLE,
.group = ACPI_PLD_GROUP(1, 2)}"
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
device ref usb3_port1 on end
end
end