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util/msrtool: Fix swapped IA32_MC3_x and IA32_MC4_x 

Registers IA32_MCi_xx are defined as architectural MSRs
since "P6 Family Processors" and should have model-agnostic
indexing.

Note that in IA32 architecture manual, names of these MSRs are
similarly swapped in the table of Intel Core Microarchitecture.
I take this is an error in the documentation only, and it got
copy-pasted across different CPU family files in the utility.

Change-Id: I227102875b5c3d6ac144ed23a3085f3c37dabd4a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26269
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2018-05-14 09:09:29 +03:00
parent 8b72aaf3f7
commit 15a971b89f
7 changed files with 37 additions and 37 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
util/msrtool/intel_atom.c
View File

@ -200,22 +200,22 @@ const struct msrdef intel_atom_msrs[] = {
{0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", { {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},

6
util/msrtool/intel_core1.c
View File

@ -70,13 +70,13 @@ const struct msrdef intel_core1_msrs[] = {
{0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", { {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {

6
util/msrtool/intel_core2_early.c
View File

@ -88,13 +88,13 @@ const struct msrdef intel_core2_early_msrs[] = {
{0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", { {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {

16
util/msrtool/intel_core2_later.c
View File

@ -1093,28 +1093,28 @@ const struct msrdef intel_core2_later_msrs[] = {
{0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", { {0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", { {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", { {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x414, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_CTL", "", { {0x414, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_CTL", "", {

16
util/msrtool/intel_nehalem.c
View File

@ -1657,28 +1657,28 @@ const struct msrdef intel_nehalem_msrs[] = {
{0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", { {0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", { {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", { {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x414, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_CTL", "", { {0x414, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_CTL", "", {

6
util/msrtool/intel_pentium3.c
View File

@ -168,13 +168,13 @@ const struct msrdef intel_pentium3_msrs[] = {
{0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{ MSR_EOT } { MSR_EOT }

12
util/msrtool/intel_pentium3_early.c
View File

@ -234,22 +234,22 @@ const struct msrdef intel_pentium3_early_msrs[] = {
{0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", { {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{ MSR_EOT } { MSR_EOT }