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mb/google/brya/variants/hades: Update GPIO configs

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Update GPIO configs based on latest schematics (revision aabe36)

Move GPP_D4->GPP_A13 (BT_DISABLE_L)
Swap GPP_E3<>GPP_E8 (WIFI_DISABLE_L and PG_PPVAR_GPU_NVVDD_X_OD)
Move GPP_A13->GPP_A20  (GSC_PCH_INT_ODL)

BUG=b:269371363
TEST=builds

Change-Id: I958e45156515cf4ce236084ec823f9329d7a063d
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Tarun Tuli 2023-04-14 19:32:24 +00:00 committed by Eric Lai
parent 7fd0c59969
commit 15dd44eedd
4 changed files with 14 additions and 13 deletions
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3
src/mainboard/google/brya/Kconfig
View file

@ -174,7 +174,8 @@ config FMDFILE
config TPM_TIS_ACPI_INTERRUPT config TPM_TIS_ACPI_INTERRUPT
int int
default 13 # GPE0_DW0_13 (GPP_A13_IRQ) default 13 if !BOARD_GOOGLE_BASEBOARD_HADES # GPE0_DW0_13 (GPP_A13_IRQ)
default 20 if BOARD_GOOGLE_BASEBOARD_HADES # GPE0_DW0_20 (GPP_A20_IRQ)
config OVERRIDE_DEVICETREE config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"

20
src/mainboard/google/brya/variants/hades/gpio.c
View file

@ -28,8 +28,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_A11, 1, DEEP), PAD_CFG_GPO(GPP_A11, 1, DEEP),
/* GPP_A12 : [] ==> EN_PP3300_LAN_X */ /* GPP_A12 : [] ==> EN_PP3300_LAN_X */
PAD_CFG_GPO(GPP_A12, 1, DEEP), PAD_CFG_GPO(GPP_A12, 1, DEEP),
/* GPP_A13 : [] ==> GSC_PCH_INT_ODL */ /* GPP_A13 : [] ==> BT_DISABLE_L */
PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), PAD_CFG_GPO(GPP_A13, 1, DEEP),
/* GPP_A14 : [] ==> EC_USB_PCH_C0_OC_ODL */ /* GPP_A14 : [] ==> EC_USB_PCH_C0_OC_ODL */
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
/* GPP_A15 : [] ==> EC_USB_PCH_C1_OC_ODL */ /* GPP_A15 : [] ==> EC_USB_PCH_C1_OC_ODL */
@ -42,8 +42,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
/* GPP_A19 : [] ==> EN_PCH_PPVAR_GPU_FBVDDQ_X */ /* GPP_A19 : [] ==> EN_PCH_PPVAR_GPU_FBVDDQ_X */
PAD_CFG_GPO(GPP_A19, 0, PLTRST), PAD_CFG_GPO(GPP_A19, 0, PLTRST),
/* GPP_A20 : [] ==> NC */ /* GPP_A20 : [] ==> GSC_PCH_INT_ODL */
PAD_NC(GPP_A20, NONE), PAD_CFG_GPI_APIC_LOCK(GPP_A20, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* GPP_A21 : [] ==> NC */ /* GPP_A21 : [] ==> NC */
PAD_NC(GPP_A21, NONE), PAD_NC(GPP_A21, NONE),
/* GPP_A22 : [] ==> NC */ /* GPP_A22 : [] ==> NC */
@ -125,8 +125,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_D2, 1, DEEP), PAD_CFG_GPO(GPP_D2, 1, DEEP),
/* GPP_D3 : [] ==> PS_NVVDD_TALERT_ODL */ /* GPP_D3 : [] ==> PS_NVVDD_TALERT_ODL */
PAD_CFG_GPI(GPP_D3, NONE, PLTRST), PAD_CFG_GPI(GPP_D3, NONE, PLTRST),
/* GPP_D4 : [] ==> BT_DISABLE_L */ /* GPP_D4 : [] ==> NC */
PAD_CFG_GPO(GPP_D4, 1, DEEP), PAD_NC(GPP_D4, NONE),
/* GPP_D5 : [] ==> GPU_CLKREQ_ODL */ /* GPP_D5 : [] ==> GPU_CLKREQ_ODL */
PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF1), PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF1),
/* GPP_D6 : [] ==> PCIE_SSD_CLKREQ_ODL */ /* GPP_D6 : [] ==> PCIE_SSD_CLKREQ_ODL */
@ -164,8 +164,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_E1, 0, PLTRST), PAD_CFG_GPO(GPP_E1, 0, PLTRST),
/* GPP_E2 : [] ==> PG_PP3300_GPU_X_OD */ /* GPP_E2 : [] ==> PG_PP3300_GPU_X_OD */
PAD_CFG_GPI_LOCK(GPP_E2, NONE, LOCK_CONFIG), PAD_CFG_GPI_LOCK(GPP_E2, NONE, LOCK_CONFIG),
/* GPP_E3 : [] ==> PG_PPVAR_GPU_NVVDD_X_OD (board rev 3 and later) */ /* GPP_E3 : [] ==> WIFI_DISABLE_L */
PAD_CFG_GPI(GPP_E3, NONE, DEEP), PAD_CFG_GPO(GPP_E3, 1, DEEP),
/* GPP_E4 : [] ==> PG_PPVAR_GPU_FBVDDQ_X_OD */ /* GPP_E4 : [] ==> PG_PPVAR_GPU_FBVDDQ_X_OD */
PAD_CFG_GPI(GPP_E4, NONE, DEEP), PAD_CFG_GPI(GPP_E4, NONE, DEEP),
/* GPP_E5 : [] ==> PG_GPU_ALLRAILS */ /* GPP_E5 : [] ==> PG_GPU_ALLRAILS */
@ -174,8 +174,8 @@ static const struct pad_config gpio_table[] = {
PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG), PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG),
/* GPP_E7 : [] ==> NC */ /* GPP_E7 : [] ==> NC */
PAD_NC(GPP_E7, NONE), PAD_NC(GPP_E7, NONE),
/* GPP_E8 : [] ==> WIFI_DISABLE_L */ /* GPP_E8 : [] ==> PG_PPVAR_GPU_NVVDD_X_OD */
PAD_CFG_GPO(GPP_E8, 1, DEEP), PAD_CFG_GPI(GPP_E8, NONE, DEEP),
/* GPP_E9 : [] ==> USB_A1_OC_ODL */ /* GPP_E9 : [] ==> USB_A1_OC_ODL */
PAD_CFG_NF_LOCK(GPP_E9, NONE, NF1, LOCK_CONFIG), PAD_CFG_NF_LOCK(GPP_E9, NONE, NF1, LOCK_CONFIG),
/* GPP_E10 : [] ==> EN_PPVAR_PEXVDD_GPU_X */ /* GPP_E10 : [] ==> EN_PPVAR_PEXVDD_GPU_X */

2
src/mainboard/google/brya/variants/hades/overridetree.cb
View file

@ -196,7 +196,7 @@ chip soc/intel/alderlake
device ref i2c3 on device ref i2c3 on
chip drivers/i2c/tpm chip drivers/i2c/tpm
register "hid" = ""GOOG0005"" register "hid" = ""GOOG0005""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A20_IRQ)"
device i2c 50 on end device i2c 50 on end
end end
end end

2
src/mainboard/google/brya/variants/hades/variant.c
View file

@ -17,7 +17,7 @@
#define GPU_3V3_PWR_EN GPP_E1 #define GPU_3V3_PWR_EN GPP_E1
#define GPU_3V3_PG GPP_E2 #define GPU_3V3_PG GPP_E2
#define NVVDD_PWR_EN GPP_E0 #define NVVDD_PWR_EN GPP_E0
#define NVVDD_PG GPP_E3 #define NVVDD_PG GPP_E8
#define PEXVDD_PWR_EN GPP_E10 #define PEXVDD_PWR_EN GPP_E10
#define PEXVDD_PG GPP_E17 #define PEXVDD_PG GPP_E17
#define FBVDD_PWR_EN GPP_A19 #define FBVDD_PWR_EN GPP_A19