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soc/intel/fsp_baytrail: use common Intel ACPI hardware definitions 

Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I1ff1517ded2d43e3790d980599e756d0d064f75c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15674
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aaron Durbin 2016-07-13 23:22:01 -05:00
parent 9e6d143a82
commit 15e439a72e
5 changed files with 26 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/intel/fsp_baytrail/Kconfig
View File

@ -23,6 +23,7 @@ if SOC_INTEL_FSP_BAYTRAIL
config CPU_SPECIFIC_OPTIONS
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32

2
src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
View File

@ -304,7 +304,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams,
pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache();
#endif
if (prev_sleep_state == 3) {
if (prev_sleep_state == ACPI_S3) {
/* S3 resume */
if ( pFspInitParams->NvsBufferPtr == NULL) {
/* If waking from S3 and no cache then. */

9
src/soc/intel/fsp_baytrail/include/soc/pmc.h
View File

@ -17,6 +17,7 @@
#ifndef _BAYTRAIL_PMC_H_
#define _BAYTRAIL_PMC_H_
#include <arch/acpi.h>
#define IOCOM1 0x3f8
@ -148,14 +149,6 @@
#define GBL_EN (1 << 5)
#define TMROF_EN (1 << 0)
#define PM1_CNT 0x04
#define SLP_EN (1 << 13)
#define SLP_TYP_SHIFT 10
#define SLP_TYP (7 << SLP_TYP_SHIFT)
#define SLP_TYP_S0 0
#define SLP_TYP_S1 1
#define SLP_TYP_S3 5
#define SLP_TYP_S4 6
#define SLP_TYP_S5 7
#define GBL_RLS (1 << 2)
#define BM_RLD (1 << 1)
#define SCI_EN (1 << 0)

27
src/soc/intel/fsp_baytrail/romstage/romstage.c
View File

@ -44,7 +44,7 @@
uint32_t chipset_prev_sleep_state(uint32_t clear)
{
/* Default to S0. */
uint32_t prev_sleep_state = 0;
uint32_t prev_sleep_state = ACPI_S0;
uint32_t pm1_sts;
uint32_t pm1_cnt;
uint32_t gen_pmcon1;
@ -58,18 +58,17 @@ uint32_t chipset_prev_sleep_state(uint32_t clear)
pm1_sts, pm1_cnt, gen_pmcon1);
if (pm1_sts & WAK_STS) {
switch ((pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
#if CONFIG_HAVE_ACPI_RESUME
case SLP_TYP_S3:
prev_sleep_state = 3;
switch (acpi_sleep_from_pm1(pm1_cnt)) {
case ACPI_S3:
if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
prev_sleep_state = ACPI_S3;
break;
#endif
case SLP_TYP_S4:
prev_sleep_state = 4;
case ACPI_S4:
prev_sleep_state = ACPI_S4;
break;
case SLP_TYP_S5:
prev_sleep_state = 5;
case ACPI_S5:
prev_sleep_state = ACPI_S5;
break;
}
/* If set Clear SLP_TYP. */
@ -79,7 +78,7 @@ uint32_t chipset_prev_sleep_state(uint32_t clear)
}
if (gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) {
prev_sleep_state = 5;
prev_sleep_state = ACPI_S5;
}
return prev_sleep_state;
@ -246,12 +245,12 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr)
post_code(0x4c);
/* if S3 resume skip ram check */
if (prev_sleep_state != 3) {
if (prev_sleep_state != ACPI_S3) {
quick_ram_check();
post_code(0x4d);
}
cbmem_was_initted = !cbmem_recovery(prev_sleep_state == 3);
cbmem_was_initted = !cbmem_recovery(prev_sleep_state == ACPI_S3);
/* Save the HOB pointer in CBMEM to be used in ramstage*/
cbmem_hob_ptr = cbmem_add (CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr));
@ -260,7 +259,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr)
handoff = romstage_handoff_find_or_add();
if (handoff != NULL)
handoff->s3_resume = (prev_sleep_state == 3);
handoff->s3_resume = (prev_sleep_state == ACPI_S3);
else
printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");

20
src/soc/intel/fsp_baytrail/smihandler.c
View File

@ -105,37 +105,37 @@ static void southbridge_smi_sleep(void)
/* Figure out SLP_TYP */
reg32 = inl(pmbase + PM1_CNT);
printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
slp_typ = (reg32 >> 10) & 7;
slp_typ = acpi_sleep_from_pm1(reg32);
/* Do any mainboard sleep handling */
mainboard_smi_sleep(slp_typ-2);
mainboard_smi_sleep(slp_typ);
#if IS_ENABLED(CONFIG_ELOG_GSMI)
/* Log S3, S4, and S5 entry */
if (slp_typ >= 5)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2);
if (slp_typ >= ACPI_S3)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
#endif
/* Next, do the deed.
*/
switch (slp_typ) {
case SLP_TYP_S0:
case ACPI_S0:
printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n");
break;
case SLP_TYP_S1:
case ACPI_S1:
printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n");
break;
case SLP_TYP_S3:
case ACPI_S3:
printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
/* Invalidate the cache before going to S3 */
wbinvd();
break;
case SLP_TYP_S4:
case ACPI_S4:
printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n");
break;
case SLP_TYP_S5:
case ACPI_S5:
printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
/* Disable all GPE */
@ -156,7 +156,7 @@ static void southbridge_smi_sleep(void)
enable_pm1_control(SLP_EN);
/* Make sure to stop executing code here for S3/S4/S5 */
if (slp_typ > 1)
if (slp_typ >= ACPI_S3)
halt();
/* In most sleep states, the code flow of this function ends at