lenovo/t530: Use native raminit over MRC blob
We now have Native raminit for both sandy/ivybridge introduced in:
7686a56 sandy/ivybridge: Native raminit.
Let us make good use of this support over using the Intel MRC blob to
initialise memory.
USB RCBA configuration data taken between base of 0x3500 up to 0x3600
from `inteltool -r`.
Remark: Note the current port is poorly tested at the moment and I am the
sole maintainer, however one less blob invites more interest for better
support. More to come hopefully.
Change-Id: I41d0ef8303dfd369c5565b823e68a6bee09c44f5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6394
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
This commit is contained in:
Edward O'Callaghan
parent
de40e0dd11
commit
1633261979
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@ -3,7 +3,7 @@ if BOARD_LENOVO_T530
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select CPU_INTEL_SOCKET_RPGA989
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select NORTHBRIDGE_INTEL_IVYBRIDGE
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select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
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select SOUTHBRIDGE_INTEL_C216
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select EC_LENOVO_PMH7
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select EC_LENOVO_H8
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@ -19,8 +19,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select SERIRQ_CONTINUOUS_MODE
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config HAVE_MRC_CACHE
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bool
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default n
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bool
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default y
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config HAVE_IFD_BIN
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bool
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@ -42,10 +42,6 @@ config MMCONF_BASE_ADDRESS
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hex
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default 0xf0000000
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config CACHE_ROM_SIZE_OVERRIDE
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hex
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default 0x800000
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config IRQ_SLOT_COUNT
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int
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default 18
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@ -33,7 +33,7 @@
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#include <cbmem.h>
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#include <console/console.h>
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#include "northbridge/intel/sandybridge/sandybridge.h"
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#include "northbridge/intel/sandybridge/raminit.h"
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#include "northbridge/intel/sandybridge/raminit_native.h"
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#include "southbridge/intel/bd82x6x/pch.h"
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#include "southbridge/intel/bd82x6x/gpio.h"
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#include <arch/cpu.h>
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@ -110,66 +110,57 @@ static void rcba_config(void)
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RCBA32(BUC) = 0;
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}
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static void init_usb(void)
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{
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const u32 rcba_dump[64] = {
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/* 3500 */ 0x20000f57, 0x20000f57, 0x2000055b, 0x20000f57,
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/* 3510 */ 0x20000f57, 0x20000153, 0x20000153, 0x2000055b,
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/* 3520 */ 0x20000153, 0x20000f57, 0x20000153, 0x20000153,
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/* 3530 */ 0x20000f51, 0x20000f57, 0x00000000, 0x00000000,
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/* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050,
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/* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630,
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/* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00001448,
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/* 35a0 */ 0x04000201, 0x00000200, 0x00000000, 0x00000000,
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/* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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};
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int i;
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/* Activate PMBAR. */
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pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
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/* Unlock registers. */
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outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
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for (i = 0; i < 64; i++)
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write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i), rcba_dump[i]);
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pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
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/* Relock registers. */
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outw (0x0000, DEFAULT_PMBASE | 0x003c);
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}
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void main(unsigned long bist)
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{
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int boot_mode = 0;
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int cbmem_was_initted;
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int s3resume = 0;
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u32 pm1_cnt;
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u16 pm1_sts;
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spd_raw_data spd[4];
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if (MCHBAR16(SSKPD) == 0xCAFE) {
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outb(0x6, 0xcf9);
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hlt ();
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}
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struct pei_data pei_data = {
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.pei_version = PEI_VERSION,
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.mchbar = DEFAULT_MCHBAR,
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.dmibar = DEFAULT_DMIBAR,
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.epbar = DEFAULT_EPBAR,
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.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
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.smbusbar = SMBUS_IO_BASE,
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.wdbbar = 0x4000000,
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.wdbsize = 0x1000,
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.hpet_address = CONFIG_HPET_ADDRESS,
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.rcba = DEFAULT_RCBABASE,
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.pmbase = DEFAULT_PMBASE,
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.gpiobase = DEFAULT_GPIOBASE,
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.thermalbase = 0xfed08000,
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.system_type = 0, // 0 Mobile, 1 Desktop/Server
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.tseg_size = CONFIG_SMM_TSEG_SIZE,
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.spd_addresses = { 0xA0, 0x00,0xA2,0x00 },
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.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
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.ec_present = 1,
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.gbe_enable = 1,
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.ddr3lv_support = 0,
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// 0 = leave channel enabled
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// 1 = disable dimm 0 on channel
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// 2 = disable dimm 1 on channel
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// 3 = disable dimm 0+1 on channel
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.dimm_channel0_disabled = 2,
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.dimm_channel1_disabled = 2,
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.max_ddr3_freq = 1600,
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.usb_port_config = {
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/* enabled usb oc pin length */
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{ 1, 0, 0x0080 }, /* P0 (left, fan side), OC 0 */
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{ 1, 1, 0x0080 }, /* P1 (left touchpad side), OC 1 */
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{ 1, 3, 0x0080 }, /* P2: dock, OC 3 */
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{ 1, 0, 0x0040 }, /* P3: wwan, no OC */
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{ 1, 0, 0x0080 }, /* P4: Wacom tablet on X230t, otherwise empty */
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{ 1, 0, 0x0080 }, /* P5: Expresscard, no OC */
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{ 0, 0, 0x0000 }, /* P6: Empty */
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{ 1, 0, 0x0080 }, /* P7: dock, no OC */
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{ 0, 0, 0x0000 }, /* P8: Empty */
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{ 1, 5, 0x0080 }, /* P9: Right (EHCI debug), OC 5 */
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{ 1, 0, 0x0040 }, /* P10: fingerprint reader, no OC */
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{ 1, 0, 0x0040 }, /* P11: bluetooth, no OC. */
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{ 1, 0, 0x0040 }, /* P12: wlan, no OC */
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{ 1, 0, 0x0080 }, /* P13: webcam, no OC */
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},
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.ddr_refresh_rate_config = 2, /* Force double refresh rate */
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};
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timestamp_init(get_initial_timestamp());
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timestamp_add_now(TS_START_ROMSTAGE);
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@ -195,6 +186,8 @@ void main(unsigned long bist)
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outl(0x00000fff, DEFAULT_GPIOBASE + GP_IO_SEL3);
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outl(0x00000f4f, DEFAULT_GPIOBASE + GP_LVL3);
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init_usb();
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/* Initialize console device(s) */
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console_init();
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@ -216,7 +209,7 @@ void main(unsigned long bist)
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if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
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if (acpi_s3_resume_allowed()) {
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printk(BIOS_DEBUG, "Resume from S3 detected.\n");
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boot_mode = 2;
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s3resume = 1;
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/* Clear SLP_TYPE. This will break stage2 but
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* we care for that when we get there.
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*/
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@ -230,31 +223,16 @@ void main(unsigned long bist)
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/* Enable SPD ROMs and DDR-III DRAM */
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enable_smbus();
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/* Prepare USB controller early in S3 resume */
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if (boot_mode == 2)
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enable_usb_bar();
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post_code(0x39);
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post_code(0x3a);
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pei_data.boot_mode = boot_mode;
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timestamp_add_now(TS_BEFORE_INITRAM);
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/* MRC.bin has a bug and sometimes halts (instead of reboot?).
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*/
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if (boot_mode != 2)
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{
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RCBA32(GCS) = RCBA32(GCS) & ~(1 << 5); /* reset */
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outw((0 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* let timer go */
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}
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memset (spd, 0, sizeof (spd));
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read_spd (&spd[0], 0x50);
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read_spd (&spd[2], 0x51);
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sdram_initialize(&pei_data);
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if (boot_mode != 2)
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{
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RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
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outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
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}
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init_dram_ddr3 (spd, 1, TCK_800MHZ, s3resume);
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timestamp_add_now(TS_AFTER_INITRAM);
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post_code(0x3c);
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@ -262,13 +240,7 @@ void main(unsigned long bist)
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rcba_config();
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post_code(0x3d);
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quick_ram_check();
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post_code(0x3e);
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MCHBAR16(SSKPD) = 0xCAFE;
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cbmem_was_initted = !cbmem_recovery(boot_mode==2);
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if (boot_mode!=2)
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save_mrc_data(&pei_data);
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#if CONFIG_HAVE_ACPI_RESUME
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/* If there is no high memory area, we didn't boot before, so
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@ -278,18 +250,14 @@ void main(unsigned long bist)
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*(u32 *)CBMEM_BOOT_MODE = 0;
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*(u32 *)CBMEM_RESUME_BACKUP = 0;
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if ((boot_mode == 2) && cbmem_was_initted) {
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if (s3resume) {
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void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
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if (resume_backup_memory) {
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*(u32 *)CBMEM_BOOT_MODE = boot_mode;
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*(u32 *)CBMEM_BOOT_MODE = 2;
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*(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
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}
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/* Magic for S3 resume */
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pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
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} else if (boot_mode == 2) {
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/* Failed S3 resume, reset to come up cleanly */
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outb(0x6, 0xcf9);
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hlt();
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} else {
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pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
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}
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