Add AMD sb600 HPET setup and some minor cleanups.
Signed-off-by: Joe Bao <zheng.bao@amd.com> Reviewed-by: Maggie Li <maggie.li@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3785 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Joe Bao
Marc Jones
parent
7a51e50582
commit
164463c551
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@ -20,11 +20,11 @@
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#ifndef SB600_CHIP_H
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#define SB600_CHIP_H
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struct southbridge_amd_sb600_config
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struct southbridge_amd_sb600_config
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{
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unsigned int ide0_enable : 1;
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unsigned int sata0_enable : 1;
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unsigned long hda_viddid;
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u32 ide0_enable : 1;
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u32 sata0_enable : 1;
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u32 hda_viddid;
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};
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struct chip_operations;
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extern struct chip_operations southbridge_amd_sb600_ops;
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@ -24,6 +24,7 @@
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#define SMBUS_IO_BASE 0x1000 /* Is it a temporary SMBus I/O base address? */
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/*SIZE 0x40 */
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static void pmio_write(u8 reg, u8 value)
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{
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outb(reg, PM_INDEX);
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@ -44,6 +45,7 @@ static u8 get_sb600_revision()
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if (dev == PCI_DEV_INVALID) {
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die("SMBUS controller not found\r\n");
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/* NOT REACHED */
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}
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return pci_read_config8(dev, 0x08);
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}
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@ -259,6 +261,7 @@ static void sb600_devices_por_init()
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if (dev == PCI_DEV_INVALID) {
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die("SMBUS controller not found\r\n");
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/* NOT REACHED */
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}
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printk_info("SMBus controller enabled, sb revision is 0x%x\r\n",
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get_sb600_revision());
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@ -317,7 +320,7 @@ static void sb600_devices_por_init()
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pci_write_config8(dev, 0x62, byte);
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/* Features Enable */
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pci_write_config32(dev, 0x64, 0x829E79BF);
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pci_write_config32(dev, 0x64, 0x829E7DBF); /* bit10: Enables the HPET interrupt. */
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/* SerialIrq Control */
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pci_write_config8(dev, 0x69, 0x90);
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@ -373,7 +376,7 @@ static void sb600_devices_por_init()
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byte |= ((1 << 1) + (1 << 6)); /*0x42, save the configuraion for port 0x80. */
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pci_write_config8(dev, 0x4A, byte);
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/* Set LPC ROM size, it has been done in sb600_lpc_init().
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/* Set LPC ROM size, it has been done in sb600_lpc_init().
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* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB;
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* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB
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* pci_write_config16(dev, 0x68, 0x000e)
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@ -382,7 +385,7 @@ static void sb600_devices_por_init()
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/* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */
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pci_write_config8(dev, 0x7C, 0x05);
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/* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM,
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/* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM,
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* TODO: I don't know what are their mean? */
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printk_info("sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
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dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
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@ -397,7 +400,7 @@ static void sb600_devices_por_init()
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pci_write_config8(dev, 0x40, 0x26);
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/* I don't know why CIM set reg0x1c as 0x11.
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/* I don't know why CIM set reg0x1c as 0x11.
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* System will block at sdram_initialize() if I set it before call sdram_initialize().
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* If it is necessary to set reg0x1c as 0x11, please call this function after sdram_initialize().
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* pci_write_config8(dev, 0x1c, 0x11);
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@ -490,8 +493,10 @@ static void sb600_pmio_por_init()
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pmio_write(0x9e, byte);
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/* rpr2.14: Hides SM bus controller Bar1 where stores HPET MMIO base address */
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/* We have to clear this bit here, otherwise the kernel hangs. */
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byte = pmio_read(0x55);
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byte |= 1 << 7;
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byte |= 1 << 1;
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pmio_write(0x55, byte);
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/* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */
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@ -550,7 +555,7 @@ static void sb600_pci_cfg()
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byte |= (1 << 3);
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pci_write_config8(dev, 0x41, byte);
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/* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
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/* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
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* generated PCIRST#. */
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byte = pmio_read(0x65);
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byte |= (1 << 4);
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@ -55,7 +55,7 @@ static int set_bits(u8 * port, u32 mask, u32 val)
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return 0;
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}
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static int codec_detect(u8 * base)
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static u32 codec_detect(u8 * base)
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{
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u32 dword;
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@ -148,7 +148,7 @@ static u32 cim_verb_data[] = {
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0x01f71ec4,
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0x01f71f01,
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};
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static unsigned find_verb(u32 viddid, u32 ** verb)
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static u32 find_verb(u32 viddid, u32 ** verb)
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{
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device_t azalia_dev = dev_find_slot(0, PCI_DEVFN(0x14, 2));
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struct southbridge_amd_sb600_config *cfg =
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@ -38,13 +38,10 @@ static void ide_init(struct device *dev)
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pci_write_config32(dev, 0x70, dword);
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/* Ultra DMA mode */
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/* enable UDMA */
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byte = pci_read_config8(dev, 0x54);
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byte |= 1 << 0;
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pci_write_config8(dev, 0x54, byte);
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byte = pci_read_config8(dev, 0x56);
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byte &= ~(7 << 0);
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byte |= 5 << 0; /* mode 5 */
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pci_write_config8(dev, 0x56, byte);
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/* Enable I/O Access&& Bus Master */
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dword = pci_read_config16(dev, 0x4);
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@ -82,14 +82,14 @@ static void sb600_lpc_read_resources(device_t dev)
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compact_resources(dev);
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}
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/**
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/**
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* @brief Enable resources for children devices
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*
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*
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* @param dev the device whos children's resources are to be enabled
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*
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*
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* This function is call by the global enable_resources() indirectly via the
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* device_operation::enable_resources() method of devices.
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*
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*
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* Indirect mutual recursion:
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* enable_childrens_resources() -> enable_resources()
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* enable_resources() -> device_operation::enable_resources()
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@ -115,7 +115,7 @@ static void sb600_lpc_enable_childrens_resources(device_t dev)
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&& (child->path.type == DEVICE_PATH_PNP)) {
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for (i = 0; i < child->resources; i++) {
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struct resource *res;
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unsigned long base, end; /* don't need long long */
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u32 base, end; /* don't need long long */
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res = &child->resource[i];
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if (!(res->flags & IORESOURCE_IO))
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continue;
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@ -24,7 +24,7 @@
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(((DEV) & 0x1F) << 15) | \
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(((FN) & 0x7) << 12))
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typedef unsigned device_t;
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typedef u32 device_t;
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#include "../../../northbridge/amd/amdk8/reset_test.c"
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@ -62,12 +62,12 @@ static void sata_init(struct device *dev)
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sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x7;
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sata_bar4 = pci_read_config16(dev, 0x20) & ~0x7;
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printk_debug("sata_bar0=%x\n", sata_bar0); /* 3030 */
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printk_debug("sata_bar1=%x\n", sata_bar1); /* 3070 */
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printk_debug("sata_bar2=%x\n", sata_bar2); /* 3040 */
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printk_debug("sata_bar3=%x\n", sata_bar3); /* 3080 */
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printk_debug("sata_bar4=%x\n", sata_bar4); /* 3000 */
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printk_debug("sata_bar5=%x\n", sata_bar5); /* e0309000 */
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/* printk_debug("sata_bar0=%x\n", sata_bar0); */ /* 3030 */
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/* printk_debug("sata_bar1=%x\n", sata_bar1); */ /* 3070 */
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/* printk_debug("sata_bar2=%x\n", sata_bar2); */ /* 3040 */
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/* printk_debug("sata_bar3=%x\n", sata_bar3); */ /* 3080 */
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/* printk_debug("sata_bar4=%x\n", sata_bar4); */ /* 3000 */
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/* printk_debug("sata_bar5=%x\n", sata_bar5); */ /* e0309000 */
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/* Program the 2C to 0x43801002 */
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dword = 0x43801002;
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@ -142,15 +142,15 @@ static void sata_init(struct device *dev)
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/* Use BAR5+0x2A8,BAR0+0x6 for Secondary Slave */
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byte = readb(sata_bar5 + 0x128);
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printk_debug("byte=%x\n", byte);
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/* printk_debug("byte=%x\n", byte); */
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byte &= 0xF;
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if (byte == 0x3) {
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outb(0xA0, sata_bar0 + 0x6);
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while ((inb(sata_bar0 + 0x6) != 0xA0)
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|| ((inb(sata_bar0 + 0x7) & 0x88) != 0)) {
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mdelay(10);
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printk_debug("0x6=%x,0x7=%x\n", inb(sata_bar0 + 0x6),
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inb(sata_bar0 + 0x7));
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/* printk_debug("0x6=%x,0x7=%x\n", inb(sata_bar0 + 0x6),
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inb(sata_bar0 + 0x7)); */
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printk_debug("drive detection fail,trying...\n");
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}
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printk_debug("Primary master device is ready\n");
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@ -41,8 +41,8 @@
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#endif
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struct ioapicreg {
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unsigned int reg;
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unsigned int value_low, value_high;
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u32 reg;
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u32 value_low, value_high;
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};
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static struct ioapicreg ioapicregvalues[] = {
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@ -89,18 +89,18 @@ static struct ioapicreg ioapicregvalues[] = {
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/* Be careful and don't write past the end... */
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};
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static void setup_ioapic(unsigned long ioapic_base)
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static void setup_ioapic(u32 ioapic_base)
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{
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int i;
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unsigned long value_low, value_high;
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volatile unsigned long *l;
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u32 value_low, value_high;
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volatile u32 *l;
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struct ioapicreg *a = ioapicregvalues;
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ioapicregvalues[0].value_high = lapicid() << (56 - 32);
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printk_debug("lapicid = %016x\n", ioapicregvalues[0].value_high);
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l = (unsigned long *)ioapic_base;
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l = (u32 *)ioapic_base;
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for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
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i++, a++) {
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@ -126,9 +126,9 @@ static void sm_init(device_t dev)
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u8 byte;
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u8 byte_old;
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u32 dword;
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unsigned long ioapic_base;
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int on;
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int nmi_option;
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u32 ioapic_base;
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u32 on;
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u32 nmi_option;
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printk_info("sm_init().\n");
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@ -143,6 +143,10 @@ static void sm_init(device_t dev)
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dword |= 1 << 9;
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pci_write_config32(dev, 0x78, dword); /* enable 0xCD6 0xCD7 */
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/* bit 10: MultiMediaTimerIrqEn */
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dword = pci_read_config8(dev, 0x64);
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dword |= 1 << 10;
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pci_write_config8(dev, 0x64, dword);
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/* enable serial irq */
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byte = pci_read_config8(dev, 0x69);
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byte |= 1 << 7; /* enable serial irq function */
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@ -191,8 +195,21 @@ static void sm_init(device_t dev)
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byte = pm_ioread(0x68);
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byte &= ~(1 << 1);
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/* 2.6 */
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byte |= 1 << 2;
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pm_iowrite(0x68, byte);
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/* 2.6 */
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byte = pm_ioread(0x65);
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byte &= ~(1 << 7);
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pm_iowrite(0x65, byte);
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/* 2.3.4 */
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byte = pm_ioread(0x52);
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byte &= ~0x2F;
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byte |= 0x8;
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pm_iowrite(0x52, byte);
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byte = pm_ioread(0x8D);
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byte &= ~(1 << 6);
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pm_iowrite(0x8D, byte);
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@ -344,9 +361,19 @@ static struct smbus_bus_operations lops_smbus_bus = {
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static void sb600_sm_read_resources(device_t dev)
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{
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struct resource *res;
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u8 byte;
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/* rpr2.14: Hides SM bus controller Bar1 where stores HPET MMIO base address */
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byte = pm_ioread(0x55);
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byte |= 1 << 7;
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pm_iowrite(0x55, byte);
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/* Get the normal pci resources of this device */
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pci_dev_read_resources(dev);
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/* pci_dev_read_resources(dev); */
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byte = pm_ioread(0x55);
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byte &= ~(1 << 7);
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pm_iowrite(0x55, byte);
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/* apic */
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res = new_resource(dev, 0x74);
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@ -357,19 +384,49 @@ static void sb600_sm_read_resources(device_t dev)
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res->gran = 8;
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res->flags = IORESOURCE_MEM | IORESOURCE_FIXED;
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res = new_resource(dev, 0x14); /* hpet */
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res->base = 0xfed00000; /* reset hpet to widely accepted address */
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res->size = 0x400;
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res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */
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res->align = 8;
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res->gran = 8;
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res->flags = IORESOURCE_MEM | IORESOURCE_FIXED;
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/* dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; */
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/* smbus */
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res = new_resource(dev, 0x10);
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res->base = 0xB00;
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res->size = 0x10;
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res->limit = 0xFFFFUL; /* res->base + res->size -1; */
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res->align = 8;
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res->gran = 8;
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res->flags = IORESOURCE_IO | IORESOURCE_FIXED;
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compact_resources(dev);
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}
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static void sb600_sm_set_resources(struct device *dev)
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{
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struct resource *res;
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u8 byte;
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pci_dev_set_resources(dev);
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/* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */
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byte = pm_ioread(0x52);
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byte |= 1 << 6;
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pm_iowrite(0x52, byte);
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res = find_resource(dev, 0x74);
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pci_write_config32(dev, 0x74, res->base | 1 << 3);
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res = find_resource(dev, 0x14);
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pci_write_config32(dev, 0x14, res->base);
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res = find_resource(dev, 0x10);
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pci_write_config32(dev, 0x10, res->base | 1);
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}
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static struct pci_operations lops_pci = {
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@ -17,12 +17,6 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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//#include <arch/io.h>
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//#include <device/device.h>
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//#include <device/pci.h>
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//#include <device/pci_ids.h>
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//#include <device/pci_ops.h>
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//#include <device/smbus_def.h>
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#include "sb600_smbus.h"
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static inline void smbus_delay(void)
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@ -32,7 +26,7 @@ static inline void smbus_delay(void)
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static int smbus_wait_until_ready(u32 smbus_io_base)
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{
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unsigned long loops;
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u32 loops;
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loops = SMBUS_TIMEOUT;
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do {
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u8 val;
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@ -48,7 +42,7 @@ static int smbus_wait_until_ready(u32 smbus_io_base)
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static int smbus_wait_until_done(u32 smbus_io_base)
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{
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unsigned long loops;
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u32 loops;
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loops = SMBUS_TIMEOUT;
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do {
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u8 val;
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@ -121,7 +115,7 @@ static int do_smbus_send_byte(u32 smbus_io_base, u32 device,
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return 0;
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}
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static int do_smbus_read_byte(u32 smbus_io_base, u32 device,
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int do_smbus_read_byte(u32 smbus_io_base, u32 device,
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u32 address)
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{
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u8 byte;
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@ -152,7 +146,7 @@ static int do_smbus_read_byte(u32 smbus_io_base, u32 device,
|
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return byte;
|
||||
}
|
||||
|
||||
static int do_smbus_write_byte(u32 smbus_io_base, u32 device,
|
||||
int do_smbus_write_byte(u32 smbus_io_base, u32 device,
|
||||
u32 address, u8 val)
|
||||
{
|
||||
u8 byte;
|
||||
|
|
@ -183,10 +177,11 @@ static int do_smbus_write_byte(u32 smbus_io_base, u32 device,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void alink_ab_indx(unsigned int reg_space, unsigned int reg_addr,
|
||||
unsigned int mask, unsigned int val)
|
||||
static void alink_ab_indx(u32 reg_space, u32 reg_addr,
|
||||
u32 mask, u32 val)
|
||||
{
|
||||
unsigned int tmp;
|
||||
u32 tmp;
|
||||
|
||||
outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX);
|
||||
tmp = inl(AB_DATA);
|
||||
|
||||
|
|
@ -201,10 +196,10 @@ static void alink_ab_indx(unsigned int reg_space, unsigned int reg_addr,
|
|||
/* space = 0: AX_INDXC, AX_DATAC
|
||||
* space = 1: AX_INDXP, AX_DATAP
|
||||
*/
|
||||
static void alink_ax_indx(unsigned int space /*c or p? */ , unsigned int axindc,
|
||||
unsigned int mask, unsigned int val)
|
||||
static void alink_ax_indx(u32 space /*c or p? */ , u32 axindc,
|
||||
u32 mask, u32 val)
|
||||
{
|
||||
unsigned int tmp;
|
||||
u32 tmp;
|
||||
|
||||
/* read axindc to tmp */
|
||||
outl(space << 30 | space << 3 | 0x30, AB_INDX);
|
||||
|
|
@ -221,6 +216,3 @@ static void alink_ax_indx(unsigned int space /*c or p? */ , unsigned int axindc,
|
|||
outl(space << 30 | space << 3 | 0x34, AB_INDX);
|
||||
outl(tmp, AB_DATA);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@
|
|||
#define AB_INDX 0xCD8
|
||||
#define AB_DATA (AB_INDX+4)
|
||||
|
||||
/* Between 1-10 seconds, We should never timeout normally
|
||||
/* Between 1-10 seconds, We should never timeout normally
|
||||
* Longer than this is just painful when a timeout condition occurs.
|
||||
*/
|
||||
#define SMBUS_TIMEOUT (100*1000*10)
|
||||
|
|
|
|||
Loading…
Reference in New Issue