soc/intel/quark: Fix I2C driver
Fix the following issues: * A raw read is described by a single read segment, don't assert. * Support reads longer than the FIFO size. * Support writes longer than the FIFO size. * Use the 400 KHz clock by default. * Remove the error displays since vboot device polling generates errors. TEST=Build and run on Galileo Gen2 Change-Id: I421ebb23989aa283b5182dcae4f8099c9ec16eee Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18029 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy
parent
2ea12e5ce0
commit
16568c7535
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corporation.
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* Copyright (C) 2016-2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -23,6 +23,7 @@
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#include <soc/i2c.h>
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#include <soc/ramstage.h>
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#include <soc/reg_access.h>
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#include <timer.h>
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static void i2c_disable(I2C_REGS *regs)
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{
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@ -46,17 +47,144 @@ static void i2c_disable(I2C_REGS *regs)
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status = regs->ic_clr_intr;
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}
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int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count)
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static int platform_i2c_write(uint32_t restart, uint8_t *tx_buffer, int length,
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uint32_t stop, uint8_t *rx_buffer, struct stopwatch *timeout)
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{
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int bytes_transferred;
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uint32_t cmd;
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I2C_REGS *regs;
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uint32_t status;
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ASSERT(tx_buffer != NULL);
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ASSERT(timeout != NULL);
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regs = get_i2c_address();
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/* Fill the FIFO with the write operation */
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bytes_transferred = 0;
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do {
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status = regs->ic_raw_intr_stat;
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/* Check for errors */
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if (status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER
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| IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) {
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i2c_disable(regs);
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return -1;
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}
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/* Check for timeout */
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if (stopwatch_expired(timeout))
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return -1;
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/* Receive any available data */
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status = regs->ic_status;
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if (rx_buffer != NULL) {
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while (status & IC_STATUS_RFNE) {
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*rx_buffer++ = (uint8_t)regs->ic_data_cmd;
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bytes_transferred++;
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status = regs->ic_status;
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}
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}
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/* Determine if space is available in the FIFO */
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if (status & IC_STATUS_TFNF) {
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/* End of the transaction? */
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cmd = IC_DATA_CMD_WRITE | *tx_buffer++ | restart;
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if (length == 1)
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cmd |= stop;
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restart = 0;
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/* Place a data byte into the FIFO */
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regs->ic_data_cmd = cmd;
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length--;
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bytes_transferred++;
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} else
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udelay(1);
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} while (length > 0);
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return bytes_transferred;
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}
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static int platform_i2c_read(uint32_t restart, uint8_t *rx_buffer, int length,
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uint32_t stop, struct stopwatch *timeout)
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{
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int bytes_transferred;
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uint32_t cmd;
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int fifo_bytes;
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uint8_t junk;
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I2C_REGS *regs;
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uint32_t status;
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ASSERT(rx_buffer != NULL);
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ASSERT(timeout != NULL);
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regs = get_i2c_address();
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/* Empty the FIFO */
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status = regs->ic_status;
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while (status & IC_STATUS_RFNE) {
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junk = (uint8_t)regs->ic_data_cmd;
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status = regs->ic_status;
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}
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/* Fill the FIFO with read commands */
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fifo_bytes = min(length, 16);
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bytes_transferred = 0;
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while (length > 0) {
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status = regs->ic_raw_intr_stat;
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/* Check for errors */
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if (status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER
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| IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) {
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i2c_disable(regs);
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return -1;
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}
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/* Check for timeout */
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if (stopwatch_expired(timeout))
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return -1;
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/* Receive any available data */
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status = regs->ic_status;
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if (status & IC_STATUS_RFNE) {
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/* Save the next data byte, removed from the RX FIFO */
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*rx_buffer++ = (uint8_t)regs->ic_data_cmd;
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bytes_transferred++;
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}
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if ((status & IC_STATUS_TFNF)
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|| ((status & IC_STATUS_RFNE) && (fifo_bytes > 0))) {
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/* End of the transaction? */
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cmd = IC_DATA_CMD_READ | restart;
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if (length == 1)
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cmd |= stop;
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restart = 0;
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/* Place a read command into the TX FIFO */
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regs->ic_data_cmd = cmd;
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if (fifo_bytes > 0)
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fifo_bytes--;
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length--;
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} else
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udelay(1);
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}
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return bytes_transferred;
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}
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int platform_i2c_transfer(unsigned int bus, struct i2c_seg *segment,
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int seg_count)
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{
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uint8_t *buffer;
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int bytes_transferred;
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uint8_t chip;
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uint32_t cmd;
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int data_bytes;
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int length;
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int read_length;
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I2C_REGS *regs;
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uint32_t restart;
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uint8_t *rx_buffer;
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uint32_t status;
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uint32_t timeout;
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uint32_t stop;
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struct stopwatch timeout;
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int total_bytes;
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uint8_t *tx_buffer;
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int tx_bytes;
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regs = get_i2c_address();
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@ -64,9 +192,8 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count)
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i2c_disable(regs);
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/* Set the slave address */
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ASSERT (count > 0);
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ASSERT (segments != NULL);
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ASSERT (segments->read == 0);
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ASSERT(seg_count > 0);
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ASSERT(segment != NULL);
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/* Clear the start and stop detection */
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status = regs->ic_clr_start_det;
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@ -75,12 +202,12 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count)
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/* Set addressing mode to 7-bit and fast mode */
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cmd = regs->ic_con;
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cmd &= ~(IC_CON_10B | IC_CON_SPEED);
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cmd |= IC_CON_RESTART_EN | IC_CON_7B | IC_CON_SPEED_100_KHz
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cmd |= IC_CON_RESTART_EN | IC_CON_7B | IC_CON_SPEED_400_KHz
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| IC_CON_MASTER_MODE;
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regs->ic_con = cmd;
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/* Set the target chip address */
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chip = segments->chip;
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chip = segment->chip;
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regs->ic_tar = chip;
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/* Enable the I2C controller */
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@ -92,86 +219,85 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count)
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status = regs->ic_clr_tx_over;
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status = regs->ic_clr_tx_abrt;
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/* Start the timeout */
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stopwatch_init_msecs_expire(&timeout, 1000);
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/* Process each of the segments */
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total_bytes = 0;
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tx_bytes = 0;
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bytes_transferred = 0;
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read_length = 0;
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buffer = NULL;
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while (count-- > 0) {
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buffer = segments->buf;
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length = segments->len;
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ASSERT (buffer != NULL);
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rx_buffer = NULL;
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restart = 0;
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while (seg_count-- > 0) {
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length = segment->len;
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total_bytes += length;
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ASSERT(segment->buf != NULL);
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ASSERT(length >= 1);
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ASSERT (segments->chip == chip);
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ASSERT(segment->chip == chip);
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if (segments->read) {
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/* Determine if this is the last segment of the transaction */
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stop = (seg_count == 0) ? IC_DATA_CMD_STOP : 0;
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/* Fill the FIFO with the necessary command bytes */
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if (segment->read) {
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/* Place read commands into the FIFO */
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read_length = length;
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while (length > 0) {
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/* Send stop bit after last byte */
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cmd = IC_DATA_CMD_READ;
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if ((count == 0) && (length == 1))
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cmd |= IC_DATA_CMD_STOP;
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rx_buffer = segment->buf;
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data_bytes = platform_i2c_read(restart, rx_buffer,
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length, stop, &timeout);
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/* Place read command in transmit FIFO */
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regs->ic_data_cmd = cmd;
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length--;
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}
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/* Return any detected error */
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if (data_bytes < 0)
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return data_bytes;
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bytes_transferred += data_bytes;
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} else {
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/* Write the data into the FIFO */
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while (length > 0) {
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/* End of the transaction? */
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cmd = IC_DATA_CMD_WRITE | *buffer++;
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if ((count == 0) && (length == 1))
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cmd |= IC_DATA_CMD_STOP;
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tx_buffer = segment->buf;
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tx_bytes += length;
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data_bytes = platform_i2c_write(restart, tx_buffer,
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length, stop, rx_buffer, &timeout);
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/* Place a data byte into the FIFO */
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regs->ic_data_cmd = cmd;
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length--;
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bytes_transferred++;
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/* Return any detected error */
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if (data_bytes < 0)
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return data_bytes;
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bytes_transferred += data_bytes;
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}
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}
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segments++;
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segment++;
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restart = IC_DATA_CMD_RESTART;
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}
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/* Wait for the end of the transaction */
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timeout = 1 * 1000 * 1000;
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if (rx_buffer != NULL)
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rx_buffer += bytes_transferred - tx_bytes;
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do {
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/* Receive any available data */
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status = regs->ic_status;
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if ((rx_buffer != NULL) && (status & IC_STATUS_RFNE)) {
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*rx_buffer++ = (uint8_t)regs->ic_data_cmd;
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bytes_transferred++;
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} else {
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status = regs->ic_raw_intr_stat;
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if (status & IC_INTR_STOP_DET)
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if ((total_bytes == bytes_transferred)
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&& (status & IC_INTR_STOP_DET))
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break;
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if ((status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER
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| IC_INTR_TX_ABRT | IC_INTR_TX_OVER))
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|| (timeout == 0)) {
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if (timeout == 0)
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printk (BIOS_ERR,
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"ERROR - I2C stop bit not received!\n");
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if (status & IC_INTR_RX_OVER)
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printk (BIOS_ERR,
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"ERROR - I2C receive overrun!\n");
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if (status & IC_INTR_RX_UNDER)
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printk (BIOS_ERR,
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"ERROR - I2C receive underrun!\n");
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if (status & IC_INTR_TX_ABRT)
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printk (BIOS_ERR,
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"ERROR - I2C transmit abort!\n");
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if (status & IC_INTR_TX_OVER)
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printk (BIOS_ERR,
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"ERROR - I2C transmit overrun!\n");
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/* Check for errors */
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if (status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER
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| IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) {
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i2c_disable(regs);
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return -1;
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}
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timeout--;
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/* Check for timeout */
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if (stopwatch_expired(&timeout))
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return -1;
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/* Delay for a while */
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udelay(1);
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} while (1);
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/* Finish reading the data bytes */
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while (read_length > 0) {
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status = regs->ic_status;
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*buffer++ = (uint8_t)regs->ic_data_cmd;
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read_length--;
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bytes_transferred++;
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status = regs->ic_status;
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}
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} while (1);
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i2c_disable(regs);
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regs->ic_tar = 0;
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/* Return the number of bytes transferred */
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return bytes_transferred;
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}
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