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coreboot-kgpe-d16
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reorder early startup so that it might work. 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2298 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich 2006-05-05 03:54:31 +00:00
parent 070a10f759
commit 1656c18d76
2 changed files with 16 additions and 8 deletions
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8
src/mainboard/olpc/rev_a/auto.c
View File

@ -157,12 +157,16 @@ static void main(unsigned long bist)
SystemPreInit();
msr_init();
cs5536_early_setup();
/* NOTE: must do this AFTER the early_setup!
* it is counting on some early MSR setup
* for cs5536
*/
cs5536_setup_onchipuart();
uart_init();
console_init();
cs5536_early_setup();
pll_reset();
cpuRegInit();

16
src/southbridge/amd/cs5536/cs5536_early_setup.c
View File

@ -232,6 +232,10 @@ static int cs5536_setup_onchipuart(void)
wrmsr(MDD_LEG_IO,msr);
}
/* note: you can't do prints in here in most cases,
* and we don't want to hang on serial, so they are
* commented out
*/
static int cs5536_early_setup(void)
{
msr_t msr;
@ -241,19 +245,19 @@ static int cs5536_early_setup(void)
msr = rdmsr(GLCP_SYS_RSTPLL);
if (msr.lo & (0x3f << 26)) {
/* PLL is already set and we are reboot from PLL reset */
print_debug("reboot from BIOS reset\n\r");
//print_debug("reboot from BIOS reset\n\r");
return;
}
print_debug("Setup idsel\r\n");
//print_debug("Setup idsel\r\n");
cs5536_setup_idsel();
print_debug("Setup iobase\r\n");
//print_debug("Setup iobase\r\n");
cs5536_usb_swapsif();
cs5536_setup_iobase();
print_debug("Setup gpio\r\n");
//print_debug("Setup gpio\r\n");
cs5536_setup_gpio();
print_debug("Setup cis_mode\r\n");
//print_debug("Setup cis_mode\r\n");
cs5536_setup_cis_mode();
print_debug("Setup smbus\r\n");
//print_debug("Setup smbus\r\n");
cs5536_enable_smbus();
dummy();
}