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soc/intel/apollolake: Switch to snake case for ModPhyIfValue 

For a unification of the naming convension, change from pascal case to
snake case style for parameter 'ModPhyIfValue'.

Change-Id: I4cdf68e65cea4ab316af969cd6a8d096b456518d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75855
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mario Scheithauer 2023-06-15 14:28:47 +02:00 committed by Jakub Czapiga
parent feafddba8e
commit 16d1eb68d2
5 changed files with 5 additions and 5 deletions
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2
src/mainboard/google/octopus/variants/baseboard/devicetree.cb
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@ -290,5 +290,5 @@ chip soc/intel/apollolake
# FSP UPD to modify the Integrated Filter (IF) value # FSP UPD to modify the Integrated Filter (IF) value
# Set it to default value: 0x12 # Set it to default value: 0x12
register "ModPhyIfValue" = "0x12" register "mod_phy_if_value" = "0x12"
end end

2
src/mainboard/starlabs/lite/variants/glk/devicetree.cb
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@ -26,7 +26,7 @@ chip soc/intel/apollolake
register "pnp_settings" = "PNP_PERF_POWER" register "pnp_settings" = "PNP_PERF_POWER"
register "ModPhyIfValue" = "0x12" register "mod_phy_if_value" = "0x12"
register "prt0_gpio" = "GPIO_PRT0_UDEF" register "prt0_gpio" = "GPIO_PRT0_UDEF"

2
src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
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@ -26,7 +26,7 @@ chip soc/intel/apollolake
register "pnp_settings" = "PNP_PERF_POWER" register "pnp_settings" = "PNP_PERF_POWER"
register "ModPhyIfValue" = "0x12" register "mod_phy_if_value" = "0x12"
register "prt0_gpio" = "GPIO_PRT0_UDEF" register "prt0_gpio" = "GPIO_PRT0_UDEF"

2
src/soc/intel/apollolake/chip.c
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@ -612,7 +612,7 @@ static void glk_fsp_silicon_init_params_cb(
/* /*
* Options to change USB3 ModPhy setting for Integrated Filter value. * Options to change USB3 ModPhy setting for Integrated Filter value.
*/ */
silconfig->ModPhyIfValue = cfg->ModPhyIfValue; silconfig->ModPhyIfValue = cfg->mod_phy_if_value;
/* /*
* Options to bump USB3 LDO voltage with 40mv. * Options to bump USB3 LDO voltage with 40mv.

2
src/soc/intel/apollolake/chip.h
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@ -190,7 +190,7 @@ struct soc_intel_apollolake_config {
* value. Default is 0 to not changing default IF value (0x12). Set * value. Default is 0 to not changing default IF value (0x12). Set
* value with the range from 0x01 to 0xff to change IF value. * value with the range from 0x01 to 0xff to change IF value.
*/ */
uint8_t ModPhyIfValue; uint8_t mod_phy_if_value;
/* Options to bump USB3 LDO voltage. Default is FALSE to not increasing /* Options to bump USB3 LDO voltage. Default is FALSE to not increasing
* LDO voltage. Set TRUE to increase LDO voltage with 40mV. * LDO voltage. Set TRUE to increase LDO voltage with 40mV.