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AGESA: BIST is already preserved 

Officialy we enter with BIST in %eax, but %ebp is old backup register.
Note that post_code() destroys %al.

Change-Id: I77b9a80aac11ae301fdda71c2a20803d7a5fb888
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18625
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-11-23 21:29:26 +02:00
parent df7ff31c59
commit 1779d534e5
1 changed files with 7 additions and 8 deletions
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15
src/cpu/amd/agesa/cache_as_ram.inc
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@ -28,7 +28,6 @@
/* /*
* XMM map: * XMM map:
* xmm0: BIST
*/ */
.code32 .code32
@ -36,6 +35,9 @@
cache_as_ram_setup: cache_as_ram_setup:
/* Preserve BIST. */
movl %eax, %ebp
post_code(0xa0) post_code(0xa0)
/* enable SSE2 128bit instructions */ /* enable SSE2 128bit instructions */
@ -45,11 +47,9 @@ cache_as_ram_setup:
orl $(3<<9), %eax orl $(3<<9), %eax
movl %eax, %cr4 movl %eax, %cr4
/* Save the BIST result */
cvtsi2sd %ebp, %xmm0
post_code(0xa1) post_code(0xa1)
/* NOTE: %ebx, %ebp are preserved in AMD_ENABLE_STACK. */
AMD_ENABLE_STACK AMD_ENABLE_STACK
/* Align the stack. */ /* Align the stack. */
@ -100,16 +100,15 @@ cache_as_ram_setup:
#endif #endif
call early_all_cores /* Calling conventions preserve BIST in %ebp. */
/* Restore the BIST result */ call early_all_cores
cvtsd2si %xmm0, %edx
/* Must maintain 16-byte stack alignment here. */ /* Must maintain 16-byte stack alignment here. */
pushl $0x0 pushl $0x0
pushl $0x0 pushl $0x0
pushl $0x0 pushl $0x0
pushl %edx /* bist */ pushl %ebp
call romstage_main call romstage_main
/* Should never see this postcode */ /* Should never see this postcode */