soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c code

This patch includes common romstage code to setup the console
and load postcar.

Fix booting regression issue on all latest IA-SOC introduced by CB:34893

Change-Id: I9da592960f20ed9742ff696198dbc028ef519ddf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Subrata Banik 2019-08-27 11:01:33 +05:30
parent da10b9224a
commit 1799011dc6
5 changed files with 5 additions and 1 deletions

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@ -21,6 +21,7 @@ bootblock-y += spi.c
bootblock-y += uart.c
romstage-y += car.c
romstage-y += ../../../cpu/intel/car/romstage.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
romstage-y += gspi.c
romstage-y += heci.c

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@ -13,6 +13,7 @@
# GNU General Public License for more details.
#
romstage-y += ../../../../cpu/intel/car/romstage.c
romstage-y += romstage.c
romstage-y += fsp_params.c
romstage-y += systemagent.c

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@ -36,6 +36,7 @@ postcar-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
romstage-y += memmap.c
romstage-y += reset.c
romstage-y += ../../../cpu/intel/car/romstage.c
romstage-y += romstage.c
romstage-y += tsc_freq.c
romstage-y += gpio_dnv.c

View File

@ -14,5 +14,6 @@
#
romstage-y += fsp_params.c
romstage-y += ../../../../cpu/intel/car/romstage.c
romstage-y += romstage.c
romstage-y += systemagent.c

View File

@ -1,4 +1,4 @@
romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += ../../../../cpu/intel/car/romstage.c
romstage-y += ../../../../cpu/intel/car/romstage.c
romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c
romstage-y += systemagent.c