northbridge/intel/haswell: Update hostbridge.asl to ASL2.0
This change updates hostbridge.asl to use ASL2.0 syntax. This increases the readability of the ASL code. TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for google/beltino. Change-Id: I0ba2da441c7b398cc7f84a7ef7a5d233b0365cbe Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -141,17 +141,16 @@ Device (MCHC)
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External (\_SB.CP00._PSS)
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Method (PSSS, 1, NotSerialized)
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{
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Store (One, Local0) /* Start at P1 */
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Store (SizeOf (\_SB.CP00._PSS), Local1)
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Local0 = One /* Start at P1 */
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Local1 = SizeOf (\_SB.CP00._PSS)
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While (LLess (Local0, Local1)) {
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While (Local0 < Local1) {
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/* Store _PSS entry Control value to Local2 */
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ShiftRight (DeRefOf (Index (DeRefOf (Index
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(\_SB.CP00._PSS, Local0)), 4)), 8, Local2)
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If (LEqual (Local2, Arg0)) {
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Return (Subtract (Local0, 1))
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Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8
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If (Local2 == Arg0) {
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Return (Local0 - 1)
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}
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Increment (Local0)
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Local0++
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}
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Return (0)
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@ -162,10 +161,10 @@ Device (MCHC)
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{
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If (\ISLP ()) {
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/* Haswell ULT PL2 = 25W */
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Return (Multiply (25, 8))
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Return (25 * 8)
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} Else {
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/* Haswell Mobile PL2 = 1.25 * PL1 */
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Return (Divide (Multiply (Arg0, 125), 100))
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Return ((Arg0 * 125) / 100)
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}
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}
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@ -183,23 +182,23 @@ Device (MCHC)
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Store ("Set TDP Down", Debug)
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/* Set CTC */
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Store (CTCD, CTCS)
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CTCS = CTCD
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/* Set TAR */
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Store (TARD, TARS)
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TARS = TARD
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/* Set PPC limit and notify OS */
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Store (PSSS (TARD), PPCM)
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PPCM = PSSS (TARD)
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PPCN ()
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/* Set PL2 */
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Store (CPL2 (CTDD), PL2V)
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PL2V = CPL2 (CTDD)
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/* Set PL1 */
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Store (CTDD, PL1V)
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PL1V = CTDD
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/* Store the new TDP Down setting */
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Store (CTCD, CTCC)
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CTCC = CTCD
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Release (CTCM)
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Return (1)
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@ -211,7 +210,7 @@ Device (MCHC)
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If (Acquire (CTCM, 100)) {
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Return (0)
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}
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If (LEqual (CTCN, CTCC)) {
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If (CTCN == CTCC) {
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Release (CTCM)
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Return (0)
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}
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@ -219,23 +218,23 @@ Device (MCHC)
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Store ("Set TDP Nominal", Debug)
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/* Set PL1 */
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Store (CTDN, PL1V)
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PL1V = CTDN
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/* Set PL2 */
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Store (CPL2 (CTDN), PL2V)
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PL2V = CPL2 (CTDN)
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/* Set PPC limit and notify OS */
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Store (PSSS (TARN), PPCM)
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PPCM = PSSS (TARN)
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PPCN ()
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/* Set TAR */
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Store (TARN, TARS)
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TARS = TARN
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/* Set CTC */
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Store (CTCN, CTCS)
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CTCS = CTCN
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/* Store the new TDP Nominal setting */
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Store (CTCN, CTCC)
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CTCC = CTCN
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Release (CTCM)
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Return (1)
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@ -244,7 +243,7 @@ Device (MCHC)
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/* Calculate PL1 value based on requested TDP */
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Method (TDPP, 1, NotSerialized)
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{
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Return (Multiply (ShiftLeft (Subtract (PUNI, 1), 2), Arg0))
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Return (((PUNI - 1) << 2) * Arg0)
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}
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/* Enable Controllable TDP to limit PL1 to requested value */
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@ -257,19 +256,19 @@ Device (MCHC)
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Store ("Enable PL1 Limit", Debug)
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/* Set _PPC to LFM */
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Store (PSSS (LFM_), Local0)
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Add (Local0, 1, PPCM)
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Local0 = PSSS (LFM_)
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PPCM = Local0 + 1
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\PPCN ()
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/* Set TAR to LFM-1 */
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Subtract (LFM_, 1, TARS)
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TARS = LFM_ - 1
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/* Set PL1 to desired value */
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Store (PL1V, SPL1)
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Store (TDPP (Arg0), PL1V)
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SPL1 = PL1V
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PL1V = TDPP (Arg0)
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/* Set PL1 CLAMP bit */
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Store (One, PL1C)
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PL1C = 1
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Release (CTCM)
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Return (1)
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@ -285,16 +284,16 @@ Device (MCHC)
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Store ("Disable PL1 Limit", Debug)
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/* Clear PL1 CLAMP bit */
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Store (Zero, PL1C)
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PL1C = 0
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/* Set PL1 to normal value */
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Store (SPL1, PL1V)
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PL1V = SPL1
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/* Set TAR to 0 */
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Store (Zero, TARS)
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TARS = 0
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/* Set _PPC to 0 */
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Store (Zero, PPCM)
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PPCM = 0
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\PPCN ()
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Release (CTCM)
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@ -426,18 +425,18 @@ Method (_CRS, 0, Serialized)
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// Fix up PCI memory region
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// Start with Top of Lower Usable DRAM
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Store (^MCHC.TLUD, Local0)
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Store (^MCHC.MEBA, Local1)
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Local0 = ^MCHC.TLUD
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Local1 = ^MCHC.MEBA
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// Check if ME base is equal
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If (LEqual (Local0, Local1)) {
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If (Local0 == Local1) {
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// Use Top Of Memory instead
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Store (^MCHC.TOM, Local0)
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Local0 = ^MCHC.TOM
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}
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Store (Local0, PMIN)
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Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
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Add(Subtract(PMAX, PMIN), 1, PLEN)
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PMIN = Local0
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PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1
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PLEN = PMAX - PMIN + 1
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Return (MCRS)
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}
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