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mb/google/nissa: Add fmd for debug FSP 

Debug FSP is ~850KiB larger than release FSP and we don't have
sufficient space for nissa flash layout.

Remove RW_LEGACY and split them into RW_SECTION_A/B so we can have a
room for it.

Note: This fmd will only used for internal testing/debugging and not for
the firmware in released devices.

BUG=b:231395098
TEST=build with CONFIG_BUILDING_WITH_DEBUG_FSP

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Idb17f003285575e80feb86bb292b95daf0f5b3b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Kangheui Won 2022-06-28 15:55:25 +10:00 committed by Felix Held
parent 9678722060
commit 1858153f10
2 changed files with 51 additions and 0 deletions
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1
src/mainboard/google/brya/Kconfig
View File

@ -150,6 +150,7 @@ config DRIVER_TPM_I2C_ADDR
config FMDFILE
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-serger.fmd" if BOARD_GOOGLE_BRASK
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-nissa-16MiB-debugfsp.fmd" if BOARD_GOOGLE_BASEBOARD_NISSA && BOARD_ROMSIZE_KB_16384 && BUILDING_WITH_DEBUG_FSP
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-nissa-16MiB.fmd" if BOARD_GOOGLE_BASEBOARD_NISSA && BOARD_ROMSIZE_KB_16384
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-nissa-32MiB.fmd" if BOARD_GOOGLE_BASEBOARD_NISSA && BOARD_ROMSIZE_KB_32768
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd"

50
src/mainboard/google/brya/chromeos-nissa-16MiB-debugfsp.fmd Normal file
View File

@ -0,0 +1,50 @@
FLASH 16M {
SI_ALL 3776K {
SI_DESC 4K
SI_ME {
CSE_LAYOUT 8K
CSE_RO 1360K
CSE_DATA 420K
# 64-KiB aligned to optimize RW erases during CSE update.
CSE_RW 1984K
}
}
SI_BIOS 12608K {
RW_SECTION_A 4180K {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 64
ME_RW_A(CBFS) 1434K
}
RW_MISC 152K {
UNIFIED_MRC_CACHE(PRESERVE) 128K {
RECOVERY_MRC_CACHE 64K
RW_MRC_CACHE 64K
}
RW_ELOG(PRESERVE) 4K
RW_SHARED 4K {
SHARED_DATA 4K
}
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 8K
}
RW_SECTION_B 4180K {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
RW_FWID_B 64
ME_RW_B(CBFS) 1434K
}
# Make WP_RO region align with SPI vendor
# memory protected range specification.
WP_RO 4M {
RO_VPD(PRESERVE) 16K
RO_GSCVD 8K
RO_SECTION {
FMAP 2K
RO_FRID 64
GBB@4K 12K
COREBOOT(CBFS)
}
}
}
}