soc/sifive/fu540: Update clock settings according SiFive bootloader
The documentation unfortunately doesn't match what SiFive uses in their FSBL. Use the same values as in FSBL to make DDR RAM work. Change-Id: I844cc41ed197333adeae495e71ea70b4a9603650 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28582 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -46,11 +46,13 @@ static struct prci_ctlr *prci = (void *)FU540_PRCI;
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#define PRCI_COREPLLCFG0_DIVQ_SHIFT 15
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#define PRCI_COREPLLCFG0_RANGE_SHIFT 18
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#define PRCI_COREPLLCFG0_BYPASS_SHIFT 24
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#define PRCI_COREPLLCFG0_FSE_SHIFT 25
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#define PRCI_COREPLLCFG0_DIVR_MASK (0x03f << PRCI_COREPLLCFG0_DIVR_SHIFT)
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#define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT)
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#define PRCI_COREPLLCFG0_DIVQ_MASK (0x007 << PRCI_COREPLLCFG0_DIVQ_SHIFT)
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#define PRCI_COREPLLCFG0_RANGE_MASK (0x07 << PRCI_COREPLLCFG0_RANGE_SHIFT)
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#define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT)
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#define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT)
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#define PRCI_DDRPLLCFG0_LOCK (1u << 31)
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#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
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@ -58,11 +60,13 @@ static struct prci_ctlr *prci = (void *)FU540_PRCI;
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#define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15
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#define PRCI_DDRPLLCFG0_RANGE_SHIFT 18
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#define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24
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#define PRCI_DDRPLLCFG0_FSE_SHIFT 25
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#define PRCI_DDRPLLCFG0_DIVR_MASK (0x03f << PRCI_DDRPLLCFG0_DIVR_SHIFT)
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#define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT)
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#define PRCI_DDRPLLCFG0_DIVQ_MASK (0x007 << PRCI_DDRPLLCFG0_DIVQ_SHIFT)
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#define PRCI_DDRPLLCFG0_RANGE_MASK (0x07 << PRCI_DDRPLLCFG0_RANGE_SHIFT)
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#define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT)
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#define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT)
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#define PRCI_DDRPLLCFG1_MASK (1u << 31)
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@ -83,18 +87,30 @@ static struct prci_ctlr *prci = (void *)FU540_PRCI;
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#define PRCI_CORECLK_DIVF 59
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#define PRCI_CORECLK_DIVQ 2
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#define PRCI_CORECLK_RANGE 4
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#define PRCI_CORECLK_BYPASS 0
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#define PRCI_CORECLK_FSE 1
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/*
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* Section 7.4.3: DDR and Ethernet Subsystem Clocking and Reset
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*
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* Unfortunately the documentation example doesn't match the HiFive
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* Unleashed board settings.
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* Configuration values taken from SiFive FSBL:
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* https://github.com/sifive/freedom-u540-c000-bootloader/blob/master/fsbl/main.c
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*
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* DDRPLL is set up for 933 MHz output frequency.
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* divr = 0, divf = 55 (3730 MHz VCO), divq = 2
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*
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* GEMGXLPLL is set up for 125 MHz output frequency.
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* divr = 0, divf = 59 (4000 MHz VCO), divq = 5 DDRPLL is set up to run at the
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* memory MT/s divided by 4.
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* divr = 0, divf = 59 (4000 MHz VCO), divq = 5
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*/
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#define PRCI_DDRCLK_DIVR 0
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#define PRCI_DDRCLK_DIVF 59
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#define PRCI_DDRCLK_DIVQ 5
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#define PRCI_DDRCLK_DIVF 55
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#define PRCI_DDRCLK_DIVQ 2
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#define PRCI_DDRCLK_RANGE 4
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#define PRCI_DDRCLK_BYPASS 0
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#define PRCI_DDRCLK_FSE 1
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// 33.33 Mhz after reset
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#define FU540_BASE_FQY 33330
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@ -108,11 +124,14 @@ static void init_coreclk(void)
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u32 c = read32(&prci->corepllcfg0);
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clrsetbits_le32(&c, PRCI_COREPLLCFG0_DIVR_MASK
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| PRCI_COREPLLCFG0_DIVF_MASK | PRCI_COREPLLCFG0_DIVQ_MASK
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| PRCI_COREPLLCFG0_RANGE_MASK | PRCI_COREPLLCFG0_BYPASS_MASK,
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| PRCI_COREPLLCFG0_RANGE_MASK | PRCI_COREPLLCFG0_BYPASS_MASK
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| PRCI_COREPLLCFG0_FSE_MASK,
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(PRCI_CORECLK_DIVR << PRCI_COREPLLCFG0_DIVR_SHIFT)
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| (PRCI_CORECLK_DIVF << PRCI_COREPLLCFG0_DIVF_SHIFT)
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| (PRCI_CORECLK_DIVQ << PRCI_COREPLLCFG0_DIVQ_SHIFT)
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| (PRCI_CORECLK_RANGE << PRCI_COREPLLCFG0_RANGE_SHIFT));
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| (PRCI_CORECLK_RANGE << PRCI_COREPLLCFG0_RANGE_SHIFT)
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| (PRCI_CORECLK_BYPASS << PRCI_COREPLLCFG0_BYPASS_SHIFT)
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| (PRCI_CORECLK_FSE << PRCI_COREPLLCFG0_FSE_SHIFT));
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write32(&prci->corepllcfg0, c);
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// wait for PLL lock
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@ -134,11 +153,14 @@ static void init_pll_ddr(void)
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u32 c = read32(&prci->ddrpllcfg0);
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clrsetbits_le32(&c, PRCI_DDRPLLCFG0_DIVR_MASK
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| PRCI_DDRPLLCFG0_DIVF_MASK | PRCI_DDRPLLCFG0_DIVQ_MASK
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| PRCI_DDRPLLCFG0_RANGE_MASK | PRCI_DDRPLLCFG0_BYPASS_MASK,
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| PRCI_DDRPLLCFG0_RANGE_MASK | PRCI_DDRPLLCFG0_BYPASS_MASK
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| PRCI_DDRPLLCFG0_FSE_MASK,
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(PRCI_DDRCLK_DIVR << PRCI_DDRPLLCFG0_DIVR_SHIFT)
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| (PRCI_DDRCLK_DIVF << PRCI_DDRPLLCFG0_DIVF_SHIFT)
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| (PRCI_DDRCLK_DIVQ << PRCI_DDRPLLCFG0_DIVQ_SHIFT)
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| (PRCI_DDRCLK_RANGE << PRCI_DDRPLLCFG0_RANGE_SHIFT));
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| (PRCI_DDRCLK_RANGE << PRCI_DDRPLLCFG0_RANGE_SHIFT)
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| (PRCI_DDRCLK_BYPASS << PRCI_DDRPLLCFG0_BYPASS_SHIFT)
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| (PRCI_DDRCLK_FSE << PRCI_DDRPLLCFG0_FSE_SHIFT));
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write32(&prci->ddrpllcfg0, c);
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// wait for PLL lock
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