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soc/intel/common/block/pcie: Select ASPM on mainboard basis 

Current the common soc code automatically selects PCIEXP_CLK_PM and
PCIEXP_L1_SUB_STATE which breaks booting Windows with a PCIE NVIDIA
graphics card attached on mainboards that do not have a CLKREQ# signal.

This is commonly used on server and workstations boards where the
additional power savings of L1 substate are not required.

Make the PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE default y but do not
select it anymore by the soc code, thus we can disable it in the
mainboard code.

Tested on CFL with Windows 10.

Change-Id: I025e13d6d8183256647e4c034e31bafa235f7eb7
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41696
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Christian Walter 2020-07-07 16:57:15 +02:00 committed by Patrick Georgi
parent 07ac2ec021
commit 18d315910a
1 changed files with 10 additions and 2 deletions
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12
src/soc/intel/common/block/pcie/Kconfig
View File

@ -1,12 +1,20 @@
config SOC_INTEL_COMMON_BLOCK_PCIE config SOC_INTEL_COMMON_BLOCK_PCIE
bool bool
select PCIEXP_ASPM select PCIEXP_ASPM
select PCIEXP_CLK_PM
select PCIEXP_COMMON_CLOCK select PCIEXP_COMMON_CLOCK
select PCIEXP_L1_SUB_STATE
help help
Intel Processor common PCIE support Intel Processor common PCIE support
if SOC_INTEL_COMMON_BLOCK_PCIE
config PCIEXP_CLK_PM
default y
config PCIEXP_L1_SUB_STATE
default y
endif # SOC_INTEL_COMMON_BLOCK_PCIE
config PCIE_DEBUG_INFO config PCIE_DEBUG_INFO
bool bool
help help