exynos5250: make lowlevel_init_c.c benign

This file has mostly (but not entirely) been replaced by coreboot
stage files. We'll keep it around for a bit longer as a reference,
but in the meantime we'll stop compiling it as to avoid comptilation
issues as we change other parts of the code.

Change-Id: I669fb1e5a1517f35979590957d581bd33df53d29
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2269
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
David Hendricks 2013-02-03 18:50:37 -08:00 committed by Ronald G. Minnich
parent 2354ef8869
commit 18ee01ed05
2 changed files with 6 additions and 3 deletions

View File

@ -12,7 +12,6 @@ bootblock-y += clock.c
romstage-y += clock.c
romstage-y += clock_init.c
romstage-y += exynos_cache.c
romstage-y += lowlevel_init_c.c
romstage-y += pinmux.c
romstage-y += power.c
romstage-y += soc.c
@ -29,7 +28,6 @@ romstage-y += dmc_init_ddr3.c
ramstage-y += clock.c
ramstage-y += clock_init.c
ramstage-y += exynos_cache.c
ramstage-y += lowlevel_init_c.c
ramstage-y += pinmux.c
ramstage-y += power.c
ramstage-y += soc.c
@ -37,7 +35,6 @@ ramstage-y += uart.c
#ramstage-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.c
#ramstage-$(CONFIG_SATA_AHCI) += sata.c
ramstage-$(CONFIG_SPL_BUILD) += lowlevel_init_c.c
exynos5250_add_bl1: $(obj)/coreboot.pre
printf " DD Adding Samsung Exynos5250 BL1\n"

View File

@ -23,6 +23,12 @@
* MA 02111-1307 USA
*/
/*
* FIXME: This file is essentially the "bootblock" leftover from U-Boot. For
* now it serves as a reference until all the resume-related stuff is added
* to the appropriate bootblock/romstage/ramstage files in coreboot.
*/
#include <common.h>
#include <config.h>
#include <cpu/samsung/exynos5-common/exynos5-common.h>