cpu/x86/sipi_vector.S: Fix reading MCU revision

Writing 0 to MSR IA32_BIOS_SIGN_ID before fetching this MSRs content
is required. This is how things are done in
cpu/intel/microcode/microcode.c.

The "Intel® 64 and IA-32 Architectures Software Developer’s Manual"
also recommends this: "It is recommended that this field be preloaded
with 0 prior to executing CPUID" (this field being %edx).

Change-Id: I24a87aff9a699ed8ab2598007c8b8562d0555ac5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

src/cpu/x86/sipi_vector.S

@@ -115,6 +115,10 @@ _start:
 	jz	microcode_done /* Bypass if no microde exists. */
 
 	/* Get the Microcode version. */
+	xorl	%eax, %eax
+	xorl	%edx, %edx
+	movl	$IA32_BIOS_SIGN_ID, %ecx
+	wrmsr
 	mov	$1, %eax
 	cpuid
 	mov	$IA32_BIOS_SIGN_ID, %ecx