atlas: control touchscreen power using ACPI

This adds the ACPI controls for power sequencing the touchscreen.

The initial setting is to keep the touchscreen powered off and in
reset.  When linux is ready to talk to the touchscreen, it powers it
on and releases reset via ACPI.

BUG=b:110286344
TEST=verified touchscreen is functional in chromeos

Change-Id: I58c42a8f09342cfe54f82ef0e6cd8ea72a5140dc
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28869
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Caveh Jalali 2018-10-01 19:37:42 -07:00 committed by Martin Roth
parent 5fdd201c17
commit 19c0ae540e
2 changed files with 10 additions and 2 deletions

View File

@ -278,6 +278,14 @@ chip soc/intel/skylake
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
register "generic.speed" = "I2C_SPEED_FAST"
register "generic.probed" = "1"
register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)"
# 2ms for load switch slew + 5 ms for touchscreen
register "generic.enable_delay_ms" = "7"
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E11)"
register "generic.reset_delay_ms" = "20"
register "generic.reset_off_delay_ms" = "1"
register "hid_desc_reg_offset" = "0xab"
device i2c 0x49 on end
end

View File

@ -154,7 +154,7 @@ static const struct pad_config gpio_table[] = {
/* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
/* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */
PAD_CFG_GPO(GPP_C22, 1, DEEP),
PAD_CFG_GPO(GPP_C22, 0, DEEP),
/* C23 : UART2_CTS# ==> PCH_WP */
PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
@ -226,7 +226,7 @@ static const struct pad_config gpio_table[] = {
/* E10 : USB2_OC1# ==> USB_C1_OC_ODL */
PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
/* E11 : USB2_OC2# ==> TOUCHSCREEN_RESET_L */
PAD_CFG_GPO(GPP_E11, 1, DEEP),
PAD_CFG_GPO(GPP_E11, 0, DEEP),
/* E12 : USB2_OC3# ==> NC */
PAD_CFG_NC(GPP_E12),
/* E13 : DDPB_HPD0 ==> USB_C1_DP_HPD */