amd/stoneyridge: Comment PCI and AcpiMmio registers in ASL
TEST=Build Grunt BUG=b:77602074 Change-Id: I24a46cc3e766ba7e9199723b042476064a698bf2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Marshall Dawson
Martin Roth
parent
33d4f73eef
commit
5fdd201c17
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@ -188,6 +188,7 @@ Method(OSFL, 0){
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OperationRegion(SMIC, SystemMemory, 0xfed80000, 0x80000)
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Field( SMIC, ByteAcc, NoLock, Preserve) {
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/* MISC registers */
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offset (0x03ee),
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U3PS, 2, /* Usb3PowerSel */
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@ -197,6 +198,7 @@ Field( SMIC, ByteAcc, NoLock, Preserve) {
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U2RP, 1, /* Usb2 Ref Clock Powerdown */
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U3RP, 1, /* Usb3 Ref Clock Powerdown */
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/* XHCI_PM registers */
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offset (0x1c00),
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, 1,
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,6,
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@ -217,70 +219,71 @@ Field( SMIC, ByteAcc, NoLock, Preserve) {
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offset (0x1c08),
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UA08, 32,
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offset (0x1e4a),
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/* AOAC Registers */
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offset (0x1e4a), /* I2C0 D3 Control */
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I0TD, 2,
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, 1,
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I0PD, 1,
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offset (0x1e4b),
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offset (0x1e4b), /* I2C0 D3 State */
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I0DS, 3,
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offset (0x1e4c),
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offset (0x1e4c), /* I2C1 D3 Control */
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I1TD, 2,
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, 1,
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I1PD, 1,
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offset (0x1e4d),
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offset (0x1e4d), /* I2C1 D3 State */
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I1DS, 3,
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offset (0x1e4e),
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offset (0x1e4e), /* I2C2 D3 Control */
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I2TD, 2,
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, 1,
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I2PD, 1,
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offset (0x1e4f),
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offset (0x1e4f), /* I2C2 D3 State */
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I2DS, 3,
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offset (0x1e50),
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offset (0x1e50), /* I2C3 D3 Control */
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I3TD, 2,
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, 1,
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I3PD, 1,
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offset (0x1e51),
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offset (0x1e51), /* I2C3 D3 State */
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I3DS, 3,
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offset (0x1e56),
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offset (0x1e56), /* UART0 D3 Control */
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U0TD, 2,
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, 1,
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U0PD, 1,
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offset (0x1e57),
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offset (0x1e57), /* UART0 D3 State */
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U0DS, 3,
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offset (0x1e58),
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offset (0x1e58), /* UART1 D3 Control */
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U1TD, 2,
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, 1,
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U1PD, 1,
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offset (0x1e59),
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offset (0x1e59), /* UART1 D3 State */
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U1DS, 3,
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offset (0x1e5e),
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offset (0x1e5e), /* SATA D3 Control */
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SATD, 2,
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, 1,
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SAPD, 1,
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offset (0x1e5f),
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offset (0x1e5f), /* SATA D3 State */
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SADS, 3,
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offset (0x1e64),
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offset (0x1e64), /* USB2 D3 Control */
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U2TD, 2,
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, 1,
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U2PD, 1,
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offset (0x1e65),
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offset (0x1e65), /* USB2 D3 State */
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U2DS, 3,
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offset (0x1e6e),
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offset (0x1e6e), /* USB3 D3 Control */
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U3TD, 2,
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, 1,
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U3PD, 1,
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offset (0x1e6f),
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offset (0x1e6f), /* USB3 D3 State */
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U3DS, 3,
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offset (0x1e70),
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offset (0x1e70), /* SD D3 Control */
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SDTD, 2,
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, 1,
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, 1,
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@ -288,10 +291,10 @@ Field( SMIC, ByteAcc, NoLock, Preserve) {
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SDRT, 1,
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SDSC, 1,
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offset (0x1e71),
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offset (0x1e71), /* SD D3 State */
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SDDS, 3,
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offset (0x1e80),
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offset (0x1e80), /* Shadow Register Request */
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, 15,
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RQ15, 1,
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, 2,
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@ -301,7 +304,7 @@ Field( SMIC, ByteAcc, NoLock, Preserve) {
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RQ24, 1,
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, 5,
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RQTY, 1,
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offset (0x1e84),
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offset (0x1e84), /* Shadow Register Status */
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, 15,
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SASR, 1, /* SATA 15 Shadow Reg Request Status Register */
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, 2,
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@ -310,13 +313,13 @@ Field( SMIC, ByteAcc, NoLock, Preserve) {
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U3SR, 1, /* USB3 23 Shadow Reg Request Status Register */
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SDSR, 1, /* SD 24 Shadow Reg Request Status Register */
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offset (0x1ea0),
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offset (0x1ea0), /* PwrGood Control */
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PG1A, 1,
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PG2_, 1,
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,1,
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U3PG, 1, /* Usb3 Power Good BIT3 */
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offset (0x1ea3), /* Power Good Control */
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offset (0x1ea3), /* PwrGood Control b[31:24] */
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PGA3, 8 ,
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}
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@ -324,35 +327,35 @@ OperationRegion(FCFG, SystemMemory, PCBA, 0x01000000)
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Field(FCFG, DwordAcc, NoLock, Preserve)
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{
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/* XHCI */
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Offset(0x00080010),
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Offset(0x00080010), /* Base address */
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XHBA, 32,
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Offset(0x0008002c),
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Offset(0x0008002c), /* Subsystem ID / Vendor ID */
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XH2C, 32,
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Offset(0x00080048),
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Offset(0x00080048), /* Indirect PCI Index Register */
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IDEX, 32,
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DATA, 32,
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Offset(0x00080054),
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Offset(0x00080054), /* PME Control / Status */
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U_PS, 2,
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/* EHCI */
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Offset(0x00090004),
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Offset(0x00090004), /* Control */
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, 1,
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EHME, 1,
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Offset(0x00090010),
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Offset(0x00090010), /* Base address */
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EHBA, 32,
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Offset(0x0009002c),
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Offset(0x0009002c), /* Subsystem ID / Vendor ID */
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EH2C, 32,
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Offset(0x00090054),
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Offset(0x00090054), /* EHCI Spare 1 */
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EH54, 8,
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Offset(0x00090064),
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Offset(0x00090064), /* Misc Control 2 */
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EH64, 8,
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Offset(0x000900c4),
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Offset(0x000900c4), /* PME Control / Status */
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E_PS, 2,
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/* LPC Bridge */
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Offset(0x000a30cb),
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Offset(0x000a30cb), /* ClientRomProtect[31:24] */
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, 7,
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AUSS, 1, /* AutoSizeStart */
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}
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