veyron: The ODT function is disabled for LPDDR3
We found that we should better keep ODT off for LPDDR3 on our boards. BRANCH=veyron BUG=chrome-os-partner:37346 TEST=Boot veyron_speedy normal Change-Id: Id158c88769cf7ed1a5127cd09bad679a2f5e6a01 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0d85725a6faedb5bdbe8731991c225c31f138599 Original-Change-Id: Iebb8e74706756508dd56b85ad87baad48893c619 Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/255381 Reviewed-on: http://review.coreboot.org/9830 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -74,5 +74,5 @@
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.dramtype = LPDDR3,
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.num_channels = 2,
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.stride = 9,
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.odt = 1
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.odt = 0,
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},
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@ -74,5 +74,5 @@
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.dramtype = LPDDR3,
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.num_channels = 2,
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.stride = 9,
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.odt = 1
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.odt = 0,
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},
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@ -74,5 +74,5 @@
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.dramtype = LPDDR3,
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.num_channels = 2,
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.stride = 9,
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.odt = 1
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.odt = 0,
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},
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@ -74,5 +74,5 @@
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.dramtype = LPDDR3,
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.num_channels = 2,
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.stride = 9,
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.odt = 1
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.odt = 0,
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},
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@ -74,5 +74,5 @@
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.dramtype = LPDDR3,
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.num_channels = 2,
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.stride = 9,
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.odt = 1
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.odt = 0,
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},
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@ -73,5 +73,5 @@
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.dramtype = LPDDR3,
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.num_channels = 1,
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.stride = 22,
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.odt = 1
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.odt = 0,
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},
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@ -74,5 +74,5 @@
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.dramtype = LPDDR3,
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.num_channels = 2,
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.stride = 9,
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.odt = 1
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.odt = 0,
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},
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@ -73,5 +73,5 @@
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.dramtype = LPDDR3,
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.num_channels = 2,
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.stride = 13,
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.odt = 1
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.odt = 0,
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},
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@ -74,5 +74,5 @@
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.dramtype = LPDDR3,
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.num_channels = 2,
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.stride = 9,
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.odt = 1
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.odt = 0,
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},
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@ -73,5 +73,5 @@
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.dramtype = LPDDR3,
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.num_channels = 2,
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.stride = 13,
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.odt = 1
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.odt = 0,
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},
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