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mainboard/intel/cannonlake_rvp: Enable SaGv config 

This patch enables SaGv on Intel CNL-Y and CNL-U RVP board

Change-Id: I8a4b8a2a365caed304935bf0d66db9a92d10c23f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31132
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ronak Kanabar 2019-01-29 01:54:38 +05:30 committed by Patrick Georgi
parent 9204355b4d
commit 19f5201463
2 changed files with 2 additions and 2 deletions
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2
src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
View File

@ -5,7 +5,7 @@ chip soc/intel/cannonlake
end end
# FSP configuration # FSP configuration
register "SaGv" = "SaGv_FixedHigh" register "SaGv" = "SaGv_Enabled"
register "ScsEmmcHs400Enabled" = "1" register "ScsEmmcHs400Enabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"

2
src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
View File

@ -5,7 +5,7 @@ chip soc/intel/cannonlake
end end
# FSP configuration # FSP configuration
register "SaGv" = "SaGv_FixedHigh" register "SaGv" = "SaGv_Enabled"
register "ScsEmmcHs400Enabled" = "1" register "ScsEmmcHs400Enabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"