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soc/intel/icelake: Make use of is_devfn_enabled() function 

1. Replace all pcidev_path_on_root() and is_dev_enabled() functions
combination with is_devfn_enabled().
2. Remove unused local variable of device structure type
(struct device *).
3. Replace pcidev_path_on_root() and dev->enabled check with
is_devfn_enabled() call.
4. Leave SATA, eMMC controller FSP UPDs at default state if
controller is not enabled and FSP UPDs are set to disable.

TEST=Able to build and boot without any regression seen on ICLRVP.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Id6861af3b5d1ce4f44b6d2109301bd4f5857f324
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik 2021-06-21 18:07:50 +05:30
parent d41a5ae489
commit 1a5d4120e6
2 changed files with 15 additions and 43 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
src/soc/intel/icelake/fsp_params.c
View File

@ -55,11 +55,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
mainboard_silicon_init_params(params);
dev = pcidev_path_on_root(SA_DEVFN_IGD);
if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled)
params->PeiGraphicsPeimInit = 1;
else
params->PeiGraphicsPeimInit = 0;
params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
params->PavpEnable = CONFIG(PAVP);
@ -68,11 +64,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->CnviBtAudioOffload = config->CnviBtAudioOffload;
/* SATA */
dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0);
if (!dev)
params->SataEnable = 0;
else {
params->SataEnable = dev->enabled;
params->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA);
if (params->SataEnable) {
params->SataMode = config->SataMode;
params->SataSalpSupport = config->SataSalpSupport;
memcpy(params->SataPortsEnable, config->SataPortsEnable,
@ -82,11 +75,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
}
/* Lan */
dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6);
if (!dev)
params->PchLanEnable = 0;
else
params->PchLanEnable = dev->enabled;
params->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE);
/* Audio */
params->PchHdaDspEnable = config->PchHdaDspEnable;
@ -166,11 +155,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(config->PcieClkSrcClkReq));
/* eMMC */
dev = pcidev_on_root(PCH_DEV_SLOT_STORAGE, 0);
if (!dev)
params->ScsEmmcEnabled = 0;
else {
params->ScsEmmcEnabled = dev->enabled;
params->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC);
if (params->ScsEmmcEnabled) {
params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
params->EmmcUseCustomDlls = config->EmmcUseCustomDlls;
if (config->EmmcUseCustomDlls == 1) {
@ -190,14 +176,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
}
/* SD */
dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 5);
if (!dev)
params->ScsSdCardEnabled = 0;
else {
params->ScsSdCardEnabled = dev->enabled;
params->SdCardPowerEnableActiveHigh =
config->SdCardPowerEnableActiveHigh;
}
params->ScsSdCardEnabled = is_devfn_enabled(PCH_DEVFN_SDCARD);
params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh;
params->Heci3Enabled = config->Heci3Enabled;
params->Device4Enable = config->Device4Enable;

22
src/soc/intel/icelake/romstage/fsp_params.c
View File

@ -13,18 +13,14 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
const struct soc_intel_icelake_config *config)
{
unsigned int i;
const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
uint32_t mask = 0;
if (CONFIG(SOC_INTEL_DISABLE_IGD) || !dev || !dev->enabled) {
/* Skip IGD initialization in FSP if device is disabled */
m_cfg->InternalGfx = 0;
m_cfg->IgdDvmt50PreAlloc = 0;
} else {
m_cfg->InternalGfx = 1;
/* Set IGD stolen size to 60MB. */
m_cfg->IgdDvmt50PreAlloc = 0xFE;
}
/*
* If IGD is enabled, set IGD stolen size to 60MB.
* Otherwise, skip IGD init in FSP.
*/
m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0;
m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
@ -34,11 +30,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->SkipMbpHob = 1;
/* If Audio Codec is enabled, enable FSP UPD */
dev = pcidev_path_on_root(PCH_DEVFN_HDA);
if (!dev)
m_cfg->PchHdaEnable = 0;
else
m_cfg->PchHdaEnable = dev->enabled;
m_cfg->PchHdaEnable = is_devfn_enabled(PCH_DEVFN_HDA);
for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
if (config->PcieRpEnable[i])