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soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKU 

Set power limits in devicetree for Tiger Lake Y-SKU based volteer
variant boards.

BUG=b:152639350
BRANCH=None
TEST=Built and tested power limits on volteer variant board.

Change-Id: If4f1226473b48365e5962df9fff29910c99007fc
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43607
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sumeet R Pawnikar 2020-07-20 15:44:59 +05:30 committed by Tim Wawrzynczak
parent 60f178db65
commit 1a62150709
3 changed files with 25 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/mainboard/google/volteer/variants/baseboard/devicetree.cb
View File

@ -211,15 +211,25 @@ chip soc/intel/tigerlake
# Enable DPTF # Enable DPTF
register "dptf_enable" = "1" register "dptf_enable" = "1"
register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 38,
.tdp_pl4 = 71,
}"
register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
.tdp_pl1_override = 15, .tdp_pl1_override = 15,
.tdp_pl2_override = 60, .tdp_pl2_override = 60,
.tdp_pl4 = 105, .tdp_pl4 = 105,
}" }"
register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ register "power_limits_config[POWER_LIMITS_Y_2_CORE]" = "{
.tdp_pl1_override = 15, .tdp_pl1_override = 9,
.tdp_pl2_override = 38, .tdp_pl2_override = 35,
.tdp_pl4 = 71, .tdp_pl4 = 66,
}"
register "power_limits_config[POWER_LIMITS_Y_4_CORE]" = "{
.tdp_pl1_override = 9,
.tdp_pl2_override = 40,
.tdp_pl4 = 83,
}" }"
register "Device4Enable" = "1" register "Device4Enable" = "1"

8
src/soc/intel/tigerlake/chip.h
View File

@ -23,9 +23,11 @@
#define MAX_HD_AUDIO_SSP_LINKS 6 #define MAX_HD_AUDIO_SSP_LINKS 6
/* The first two are for TGL-U */ /* The first two are for TGL-U */
#define POWER_LIMITS_U_4_CORE 0 #define POWER_LIMITS_U_2_CORE 0
#define POWER_LIMITS_U_2_CORE 1 #define POWER_LIMITS_U_4_CORE 1
#define POWER_LIMITS_MAX 2 #define POWER_LIMITS_Y_2_CORE 2
#define POWER_LIMITS_Y_4_CORE 3
#define POWER_LIMITS_MAX 4
/* /*
* Enable External V1P05 Rail in: BIT0:S0i1/S0i2, * Enable External V1P05 Rail in: BIT0:S0i1/S0i2,

6
src/soc/intel/tigerlake/systemagent.c
View File

@ -84,6 +84,12 @@ void soc_systemagent_init(struct device *dev)
case PCI_DEVICE_ID_INTEL_TGL_ID_U_4_2: case PCI_DEVICE_ID_INTEL_TGL_ID_U_4_2:
soc_config = &config->power_limits_config[POWER_LIMITS_U_4_CORE]; soc_config = &config->power_limits_config[POWER_LIMITS_U_4_CORE];
break; break;
case PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2:
soc_config = &config->power_limits_config[POWER_LIMITS_Y_2_CORE];
break;
case PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2:
soc_config = &config->power_limits_config[POWER_LIMITS_Y_4_CORE];
break;
default: default:
printk(BIOS_ERR, "TGL: unknown SA ID: 0x%4x, skipping power limits " printk(BIOS_ERR, "TGL: unknown SA ID: 0x%4x, skipping power limits "
"configuration\n", sa_pci_id); "configuration\n", sa_pci_id);