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nb/intel/i945: Clean up includes 

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I0e5f102d75647c9c184cb7422af30c9196503882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes Haouas 2022-10-07 10:41:42 +02:00 committed by Martin Roth
parent 4944609bd0
commit 1a847a11be
3 changed files with 7 additions and 11 deletions
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1
src/northbridge/intel/i945/errata.c
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@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <stdint.h>
#include "i945.h"
#include "raminit.h"

11
src/northbridge/intel/i945/i945.h
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@ -3,10 +3,11 @@
#ifndef NORTHBRIDGE_INTEL_I945_H
#define NORTHBRIDGE_INTEL_I945_H
#define DEFAULT_X60BAR 0xfed13000
#include <northbridge/intel/common/fixed_bars.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
#define DEFAULT_X60BAR 0xfed13000
/* Everything below this line is ignored in the DSDT */
#ifndef __ACPI__
@ -86,12 +87,6 @@
#define BSM 0x5c
#define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */
/*
* MCHBAR
*/
#include <northbridge/intel/common/fixed_bars.h>
/* Chipset Control Registers */
#define FSBPMC3 0x40 /* 32bit */
#define FSBPMC4 0x44 /* 32bit */

6
src/northbridge/intel/i945/romstage.c
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@ -1,12 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <stdint.h>
#include <cf9_reset.h>
#include <arch/romstage.h>
#include <cf9_reset.h>
#include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
#include <southbridge/intel/common/pmclib.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
#include <stdint.h>
__weak void mainboard_lpc_decode(void)
{