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arm64: Initialize exception stack 

Initialize the exception stack on stage_entry

BUG=chrome-os-partner:31515
BRANCH=None
TEST=Exception handling works fine

Change-Id: I66b4e73e77ad746e891cb2ae6662fbf0531f9d8a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a21d0a432e1742fd8b36b3f8fc7748152f7d74d2
Original-Change-Id: I0b6fb95c660c68fb47a30e905acb910b0e2eafea
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/213673
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8999
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Furquan Shaikh 2014-08-21 12:52:06 -07:00 committed by Patrick Georgi
parent 4e994c0219
commit 1af7b5ddf1
1 changed files with 12 additions and 0 deletions
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12
src/arch/arm64/stage_entry.S
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@ -55,6 +55,16 @@ ENTRY(arm64_el3_startup)
and x0, x0, x1 and x0, x0, x1
msr SCR_EL3, x0 msr SCR_EL3, x0
/* Initialize SP_EL3 as exception stack */
ldr x0, .exception_stack_top
cmp x0, #0
b.eq 2f
msr SPSel, #1
isb
mov sp, x0
2:
/* Have stack pointer use SP_EL0. */ /* Have stack pointer use SP_EL0. */
msr SPSel, #0 msr SPSel, #0
isb isb
@ -81,6 +91,8 @@ ENTRY(arm64_el3_startup)
* to the Kconfig option for cpu0. However, this code can be relocated * to the Kconfig option for cpu0. However, this code can be relocated
* and reused to start up secondary cpus. * and reused to start up secondary cpus.
*/ */
.exception_stack_top:
.quad CONFIG_EXCEPTION_STACK_TOP
.stack_top: .stack_top:
.quad _estack .quad _estack
.entry: .entry: