mb/intel/shadowmountain: Add bootblock and verstage code
This patch includes the bootblock and verstage changes for shadowmountain board. BUG=b:175808146 TEST= Build and boot shadowmountain board till early romstage. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I5f805baf42203306ff10e91a258d9117dd986c4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
This commit is contained in:
V Sowmya
Patrick Georgi
parent
72463720a2
commit
1b150cb000
9 changed files with 282 additions and 0 deletions
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@ -3,9 +3,39 @@ if BOARD_INTEL_SHADOWMOUNTAIN
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_32768
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_HID
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select DRIVERS_INTEL_DPTF
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select DRIVERS_INTEL_PMC
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select DRIVERS_SPI_ACPI
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select DRIVERS_USB_ACPI
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_BOARDID
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select EC_GOOGLE_CHROMEEC_SKUID
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select EC_GOOGLE_CHROMEEC_LPC
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_CHROMEOS
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select SOC_INTEL_ALDERLAKE
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config CHROMEOS
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select GBB_FLAG_FORCE_DEV_SWITCH_ON
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select GBB_FLAG_FORCE_DEV_BOOT_USB
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select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
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select GBB_FLAG_FORCE_MANUAL_RECOVERY
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select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
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config VBOOT
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select VBOOT_LID_SWITCH
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select VBOOT_MOCK_SECDATA
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select HAS_RECOVERY_MRC_CACHE
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config DIMM_SPD_SIZE
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int
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default 512
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config DEVICETREE
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string
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default "variants/baseboard/devicetree.cb"
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13
src/mainboard/intel/shadowmountain/Makefile.inc
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13
src/mainboard/intel/shadowmountain/Makefile.inc
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@ -0,0 +1,13 @@
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## SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += bootblock.c
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bootblock-$(CONFIG_CHROMEOS) += chromeos.c
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verstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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subdirs-y += variants/baseboard
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
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10
src/mainboard/intel/shadowmountain/bootblock.c
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10
src/mainboard/intel/shadowmountain/bootblock.c
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@ -0,0 +1,10 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <bootblock_common.h>
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void bootblock_mainboard_early_init(void)
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{
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variant_configure_early_gpio_pads();
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}
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34
src/mainboard/intel/shadowmountain/chromeos.c
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34
src/mainboard/intel/shadowmountain/chromeos.c
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@ -0,0 +1,34 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <boot/coreboot_tables.h>
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#include <gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {
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{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
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{-1, ACTIVE_HIGH, 0, "power"},
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{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
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{GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW),
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"EC in RW"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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int get_write_protect_state(void)
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{
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/* Read PCH_WP GPIO. */
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return gpio_get(GPIO_PCH_WP);
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}
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void mainboard_chromeos_acpi_generate(void)
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{
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const struct cros_gpio *gpios;
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size_t num;
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gpios = variant_cros_gpios(&num);
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chromeos_acpi_gpio_generate(gpios, num);
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}
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@ -0,0 +1,3 @@
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## SPDX-License-Identifier: GPL-2.0-or-later
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bootblock-y += early_gpio.c
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@ -1,5 +1,101 @@
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chip soc/intel/alderlake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "pmc_gpe0_dw0" = "GPP_C"
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register "pmc_gpe0_dw1" = "GPP_D"
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register "pmc_gpe0_dw2" = "GPP_E"
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Graphics
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device pci 04.0 on end # DPTF
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device pci 05.0 on end # IPU
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device pci 06.0 on end # PEG60
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device pci 07.0 on end # TBT_PCIe0
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device pci 07.1 on end # TBT_PCIe1
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device pci 07.2 on end # TBT_PCIe2
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device pci 07.3 on end # TBT_PCIe3
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device pci 08.0 off end # GNA
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device pci 09.0 off end # NPK
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device pci 0a.0 off end # Crash-log SRAM
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device pci 0d.0 on end # USB xHCI
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device pci 0d.1 on end # USB xDCI (OTG)
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device pci 0d.2 on end
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device pci 0d.3 on end # TBT DMA1
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device pci 0e.0 off end # VMD
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device pci 10.0 off end
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device pci 10.1 off end
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device pci 10.2 on end # CNVi: BT
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device pci 10.6 off end # THC0
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device pci 10.7 off end # THC1
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device pci 11.0 off end
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device pci 11.1 off end
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device pci 11.2 off end
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device pci 11.3 off end
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device pci 11.4 off end
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device pci 11.5 off end
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device pci 12.0 off end # SensorHUB
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device pci 12.5 off end
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device pci 12.6 off end # GSPI2
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device pci 13.0 off end # GSPI3
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device pci 13.1 off end
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device pci 14.0 on end # USB3.1 xHCI
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device pci 14.1 off end # USB3.1 xDCI
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device pci 14.2 off end # Shared RAM
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device pci 14.3 on end # CNVi: WiFi
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device pci 15.0 on end # I2C0
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device pci 15.1 on end # I2C1
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device pci 15.2 on end # I2C2
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device pci 15.3 on end # I2C3
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device pci 16.0 off end # HECI1
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device pci 16.1 off end # HECI2
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device pci 16.2 off end # CSME
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device pci 16.3 off end # CSME
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device pci 16.4 off end # HECI3
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device pci 16.5 off end # HECI4
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device pci 17.0 on end # SATA
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device pci 19.0 off end # I2C4
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device pci 19.1 on end # I2C5
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device pci 19.2 off end # UART2
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device pci 1c.0 off end # RP1
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device pci 1c.1 off end # RP2
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device pci 1c.2 off end # RP3
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device pci 1c.3 off end # RP4
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device pci 1c.4 on end # RP5
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device pci 1c.5 off end # RP6
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device pci 1c.6 off end # RP7
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device pci 1c.7 on end # RP8
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device pci 1d.0 on end # RP9
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device pci 1d.1 off end # RP10
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device pci 1d.2 off end # RP11
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device pci 1d.3 off end # RP12
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device pci 1e.0 on end # UART0
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device pci 1e.1 off end # UART1
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device pci 1e.2 on end # GSPI0
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device pci 1e.3 off end # GSPI1
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device pci 1f.0 on
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end # eSPI
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device pci 1f.1 on end # P2SB
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device pci 1f.2 hidden end # PMC
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device pci 1f.3 on end # Intel Audio SNDW
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # SPI
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device pci 1f.6 off end # GbE
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end
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end
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@ -0,0 +1,53 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* UART0 RX */
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
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/* UART0 TX */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
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/* A7 : MEM_STRAP_0 */
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PAD_CFG_GPI(GPP_A7, NONE, DEEP),
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/* A17 : MEM_CH_SEL */
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PAD_CFG_GPI(GPP_A17, NONE, DEEP),
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/* A19 : MEM_STRAP_2 */
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PAD_CFG_GPI(GPP_A19, NONE, DEEP),
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/* A20 : MEM_STRAP_1 */
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PAD_CFG_GPI(GPP_A20, NONE, DEEP),
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/* B11 : PCH_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
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/* C0 : EN_PP3300_WLAN */
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PAD_CFG_GPO(GPP_C0, 1, DEEP),
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/* C3 : H1_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_C3, NONE, PLTRST, LEVEL, INVERT),
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/* D10 : EN_PP3300_WWAN */
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PAD_CFG_GPO(GPP_D10, 1, DEEP),
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/* E10 : PCH_GSPI0_H1_TPM_CS_L */
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PAD_CFG_NF(GPP_E10, NONE, DEEP, NF7),
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/* E11 : PCH_GSPI0_H1_TPM_CLK */
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PAD_CFG_NF(GPP_E11, NONE, DEEP, NF7),
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/* E12 : PCH_GSPIO_H1_TPM_MISO */
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PAD_CFG_NF(GPP_E12, NONE, DEEP, NF7),
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/* E13 : PCH_GSPI0_H1_TPM_MOSI_STRAP */
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PAD_CFG_NF(GPP_E13, NONE, DEEP, NF7),
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/* F14 : WLAN_PERST_L */
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PAD_CFG_GPO(GPP_F14, 1, DEEP),
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/* F20 : WWAN_RST_ODL
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To meet timing constraints - drive reset low.
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Deasserted in ramstage. */
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PAD_CFG_GPO(GPP_F20, 0, DEEP),
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};
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void variant_configure_early_gpio_pads(void)
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{
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gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
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}
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@ -0,0 +1,24 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __BASEBOARD_GPIO_H__
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#define __BASEBOARD_GPIO_H__
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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/* EC in RW */
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#define GPIO_EC_IN_RW GPP_A8
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/* BIOS Flash Write Protect */
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#define GPIO_PCH_WP GPP_B11
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/* EC wake is LAN_WAKE# */
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#define GPE_EC_WAKE GPE0_LAN_WAK
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/* EC sync IRQ */
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#define EC_SYNC_IRQ GPP_C6_IRQ
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/* eSPI virtual wire reporting */
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#define EC_SCI_GPI GPE0_ESPI
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#endif /* BASEBOARD_GPIO_H */
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@ -0,0 +1,19 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __BASEBOARD_VARIANTS_H__
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#define __BASEBOARD_VARIANTS_H__
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#include <soc/gpio.h>
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#include <soc/meminit.h>
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#include <stddef.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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/*
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* The next set of functions return the gpio table and fill in the number of
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* entries for each table.
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*/
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const struct cros_gpio *variant_cros_gpios(size_t *num);
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void variant_configure_early_gpio_pads(void);
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#endif /* __BASEBOARD_VARIANTS_H__ */
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