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arch/riscv: Enable unaligned load handling 

Change-Id: If1c63971335a6e2963e01352acfa4bd0c1d86bc2
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15590
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Jonathan Neuschäfer 2016-07-07 20:53:29 +02:00 committed by Ronald G. Minnich
parent 91ef21df62
commit 1b1d4b7ae6
2 changed files with 3 additions and 3 deletions
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2
src/arch/riscv/include/arch/exception.h
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@ -55,7 +55,7 @@ static inline void exception_init(void)
void trap_handler(trapframe* tf);
void handle_supervisor_call(trapframe* tf);
void handleMisalignedLoad(trapframe *tf);
void handle_misaligned_load(trapframe *tf);
void handle_misaligned_store(trapframe *tf);
#endif

4
src/arch/riscv/trap_handler.c
View File

@ -118,7 +118,7 @@ void trap_handler(trapframe *tf) {
break;
case 4:
printk(BIOS_DEBUG, "Trap: Load address misaligned\n");
//handleMisalignedLoad(tf);
handle_misaligned_load(tf);
break;
case 5:
printk(BIOS_DEBUG, "Trap: Load access fault\n");
@ -161,7 +161,7 @@ void trap_handler(trapframe *tf) {
while(1);
}
void handleMisalignedLoad(trapframe *tf) {
void handle_misaligned_load(trapframe *tf) {
printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf);
printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]);
insn_t faultingInstruction = 0;