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soc/{samsung,sifive}: Fix typos 

Change-Id: Ib370f04a63160e2a8a1b06620e659feb45c8f552
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
This commit is contained in:
Elyes HAOUAS 2020-02-19 20:48:29 +01:00 committed by Patrick Georgi
parent e9f86c1016
commit 1b296ee3b8
2 changed files with 2 additions and 2 deletions
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2
src/soc/samsung/exynos5420/spi.c
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@ -101,7 +101,7 @@ static void exynos_spi_init(struct exynos_spi *regs)
// CPOL: Active high.
clrbits32(&regs->ch_cfg, SPI_CH_CPOL_L);
// Clear rx and tx channel if set priveously.
// Clear rx and tx channel if set previously.
clrbits32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
setbits32(&regs->swap_cfg,

2
src/soc/sifive/fu540/clock.c
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@ -104,7 +104,7 @@ static void configure_pll(u32 *reg, const struct pll_settings *s)
* Set coreclk according to the SiFive FU540-C000 Manual
* https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/
*
* Section 7.1 recommends a frequency of 1.0 GHz (up to 1.5 Ghz is possible)
* Section 7.1 recommends a frequency of 1.0 GHz (up to 1.5 GHz is possible)
*
* Section 7.4.2 provides the necessary values:
* For example, to setup COREPLL for 1 GHz operation, program divr = 0 (x1),