soc/amd: rename agesa_write_acpi_tables to soc_acpi_write_tables

It's not the AGESA code that generates most of the ACPI tables, so
rename the function. This also aligns the other SoCs more with Genoa.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b2e6c4cb7139c8bde01b4440ab2e923a1086827
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80217
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/cezanne/agesa_acpi.c

@@ -7,8 +7,8 @@
 #include <soc/acpi.h>
 #include <types.h>
 
-uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current,
-				  acpi_rsdp_t *rsdp)
+uintptr_t soc_acpi_write_tables(const struct device *device, uintptr_t current,
+				acpi_rsdp_t *rsdp)
 {
 	/* TODO: look into adding CRAT */
 

src/soc/amd/cezanne/chip.c

@@ -35,7 +35,7 @@ struct device_operations cezanne_pci_domain_ops = {
 
 static void soc_init(void *chip_info)
 {
-	default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables;
+	default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables;
 
 	amd_fsp_silicon_init();
 

src/soc/amd/cezanne/include/soc/acpi.h

@@ -10,7 +10,7 @@
 
 #define ACPI_SCI_IRQ 9
 
-uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current,
-				  acpi_rsdp_t *rsdp);
+uintptr_t soc_acpi_write_tables(const struct device *device, uintptr_t current,
+				acpi_rsdp_t *rsdp);
 
 #endif /* AMD_CEZANNE_ACPI_H */

src/soc/amd/glinda/agesa_acpi.c

@@ -9,8 +9,8 @@
 #include <soc/acpi.h>
 #include <types.h>
 
-uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current,
-				  acpi_rsdp_t *rsdp)
+uintptr_t soc_acpi_write_tables(const struct device *device, uintptr_t current,
+				acpi_rsdp_t *rsdp)
 {
 	/* TODO: look into adding CRAT */
 

src/soc/amd/glinda/chip.c

@@ -37,7 +37,7 @@ struct device_operations glinda_pci_domain_ops = {
 
 static void soc_init(void *chip_info)
 {
-	default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables;
+	default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables;
 
 	amd_fsp_silicon_init();
 

src/soc/amd/glinda/include/soc/acpi.h

@@ -12,7 +12,7 @@
 
 #define ACPI_SCI_IRQ 9
 
-uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current,
-				  acpi_rsdp_t *rsdp);
+uintptr_t soc_acpi_write_tables(const struct device *device, uintptr_t current,
+				acpi_rsdp_t *rsdp);
 
 #endif /* AMD_GLINDA_ACPI_H */

src/soc/amd/mendocino/agesa_acpi.c

@@ -9,8 +9,8 @@
 #include <soc/acpi.h>
 #include <types.h>
 
-uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current,
-				  acpi_rsdp_t *rsdp)
+uintptr_t soc_acpi_write_tables(const struct device *device, uintptr_t current,
+				acpi_rsdp_t *rsdp)
 {
 	/* TODO: look into adding CRAT */
 

src/soc/amd/mendocino/chip.c

@@ -35,7 +35,7 @@ struct device_operations mendocino_pci_domain_ops = {
 
 static void soc_init(void *chip_info)
 {
-	default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables;
+	default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables;
 
 	amd_fsp_silicon_init();
 

src/soc/amd/mendocino/include/soc/acpi.h

@@ -10,7 +10,7 @@
 
 #define ACPI_SCI_IRQ 9
 
-uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current,
-				  acpi_rsdp_t *rsdp);
+uintptr_t soc_acpi_write_tables(const struct device *device, uintptr_t current,
+				acpi_rsdp_t *rsdp);
 
 #endif /* AMD_MENDOCINO_ACPI_H */

src/soc/amd/phoenix/agesa_acpi.c

@@ -10,8 +10,8 @@
 #include <soc/acpi.h>
 #include <types.h>
 
-uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current,
-				  acpi_rsdp_t *rsdp)
+uintptr_t soc_acpi_write_tables(const struct device *device, uintptr_t current,
+				acpi_rsdp_t *rsdp)
 {
 	/* TODO: look into adding CRAT */
 

src/soc/amd/phoenix/chip.c

@@ -37,7 +37,7 @@ struct device_operations phoenix_pci_domain_ops = {
 
 static void soc_init(void *chip_info)
 {
-	default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables;
+	default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables;
 
 	amd_fsp_silicon_init();
 

src/soc/amd/phoenix/include/soc/acpi.h

@@ -12,7 +12,7 @@
 
 #define ACPI_SCI_IRQ 9
 
-uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current,
-				  acpi_rsdp_t *rsdp);
+uintptr_t soc_acpi_write_tables(const struct device *device, uintptr_t current,
+				acpi_rsdp_t *rsdp);
 
 #endif /* AMD_PHOENIX_ACPI_H */

src/soc/amd/picasso/agesa_acpi.c

@@ -539,8 +539,8 @@ static unsigned long acpi_fill_crat(struct acpi_crat_header *crat, unsigned long
 	return current;
 }
 
-uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current,
-				  acpi_rsdp_t *rsdp)
+uintptr_t soc_acpi_write_tables(const struct device *device, uintptr_t current,
+				acpi_rsdp_t *rsdp)
 {
 	struct acpi_crat_header *crat;
 

src/soc/amd/picasso/chip.c

@@ -36,7 +36,7 @@ struct device_operations picasso_pci_domain_ops = {
 
 static void soc_init(void *chip_info)
 {
-	default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables;
+	default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables;
 
 	amd_fsp_silicon_init();
 

src/soc/amd/picasso/include/soc/acpi.h

@@ -10,7 +10,7 @@
 
 #define ACPI_SCI_IRQ 9
 
-uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current,
-				  acpi_rsdp_t *rsdp);
+uintptr_t soc_acpi_write_tables(const struct device *device, uintptr_t current,
+				acpi_rsdp_t *rsdp);
 
 #endif /* AMD_PICASSO_ACPI_H */

src/soc/amd/stoneyridge/northbridge.c

@@ -131,9 +131,9 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest)
 	return (unsigned long)current;
 }
 
-static unsigned long agesa_write_acpi_tables(const struct device *device,
-					     unsigned long current,
-					     acpi_rsdp_t *rsdp)
+static unsigned long soc_acpi_write_tables(const struct device *device,
+					   unsigned long current,
+					   acpi_rsdp_t *rsdp)
 {
 	acpi_srat_t *srat;
 	acpi_slit_t *slit;
@@ -210,7 +210,7 @@ struct device_operations stoneyridge_northbridge_operations = {
 	.enable_resources = pci_dev_enable_resources,
 	.init		  = northbridge_init,
 	.acpi_fill_ssdt   = acpi_fill_root_complex_tom,
-	.write_acpi_tables = agesa_write_acpi_tables,
+	.write_acpi_tables = soc_acpi_write_tables,
 };
 
 /*