soc/intel/cannonlake: Add Pch iSCLK programming

In order to reduce BOM cost and board area for imaging solution, the
sensor requires a 19.2/24MHz reference clock from PCH. In addition to
that, having PCH to supply the sensor reference clock will prevent
dependency on CPU power management and also avoid level shifter cost.

Pch iSCLK is only required for CNP-LP with the camera sensor on the
platform.

BUG=None
TEST=Boot up into OS and read back PCH iSCLK programming through
iotools.

Change-Id: I28c97a75f2a7f5122a20c8b8f0f2671037a7eca6
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23367
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/cannonlake/chip.h

@@ -263,6 +263,9 @@ struct soc_intel_cannonlake_config {
 
 	/* I2C bus configuration */
 	struct dw_i2c_bus_config i2c[CANNONLAKE_I2C_DEV_MAX];
+
+	/* Enable Pch iSCLK */
+	uint8_t pch_isclk;
 };
 
 typedef struct soc_intel_cannonlake_config config_t;

src/soc/intel/cannonlake/finalize.c

@@ -37,6 +37,12 @@
 #define PCR_PSFX_T0_SHDW_PCIEN	0x1C
 #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS	(1 << 8)
 
+#define CAMERA1_CLK		0x8000 /* Camera 1 Clock */
+#define CAMERA2_CLK		0x8080 /* Camera 2 Clock */
+#define CAM_CLK_EN		(1 << 1)
+#define MIPI_CLK		(1 << 0)
+#define HDPLL_CLK		(0 << 0)
+
 static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask)
 {
 	uint32_t reg32;
@@ -64,24 +70,36 @@ static void disable_sideband_access(void)
 }
 
 static void pch_disable_heci(void)
+{
+	pcr_or32(PID_PSF1, PSF_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN,
+		PCR_PSFX_T0_SHDW_PCIEN_FUNDIS);
+	disable_sideband_access();
+}
+
+static void pch_enable_isclk(void)
+{
+	pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK);
+	pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK);
+}
+
+static void pch_handle_sideband(config_t *config)
 {
 	device_t dev = PCH_DEV_P2SB;
 
-	/*
-	 * if p2sb device 1f.1 is not present or hidden in devicetree
-	 * p2sb device becomes NULL
-	 */
 	if (!dev)
 		return;
 
+	if (config->HeciEnabled && !config->pch_isclk)
+		return;
+
 	/* unhide p2sb device */
 	pci_write_config8(dev, PCH_P2SB_E0 + 1, 0);
 
-	/* disable heci#1 */
-	pcr_or32(PID_PSF1, PSF_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN,
-		PCR_PSFX_T0_SHDW_PCIEN_FUNDIS);
+	if (config->HeciEnabled == 0)
+		pch_disable_heci();
 
-	disable_sideband_access();
+	if (config->pch_isclk)
+		pch_enable_isclk();
 
 	/* hide p2sb device */
 	pci_write_config8(dev, PCH_P2SB_E0 + 1, 1);
@@ -124,9 +142,7 @@ static void pch_finalize(void)
 		write32(pmcbase + CPPMVRIC, reg32);
 	}
 
-	/* we should disable Heci1 based on the devicetree policy */
-	if (config->HeciEnabled == 0)
-		pch_disable_heci();
+	pch_handle_sideband(config);
 }
 
 static void soc_finalize(void *unused)

src/soc/intel/cannonlake/include/soc/pcr_ids.h

@@ -25,6 +25,7 @@
 #define PID_GPIOCOM0	0x6e
 #define PID_DMI		0x88
 #define PID_PSTH	0x89
+#define PID_ISCLK	0xad
 #define PID_PSF1	0xba
 #define PID_PSF2	0xbb
 #define PID_PSF3	0xbc