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soc/intel/apollolake: Add EMMC DLL API 

Starting from 136_30,FSP supports to update all the SDIO DLL 
programming value through silicon init upd. Implement the interface 
to pass board specific programming value to fsp silicon init.

Change-Id: Ifd901148f3f7f89f966217491c661ec346337c38
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://chromium.devtools.intel.com/7372
Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com>
Tested-by: Petrov, Andrey <andrey.petrov@intel.com>
Reviewed-on: https://chromium.devtools.intel.com/7585
Reviewed-on: https://review.coreboot.org/15084
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Zhao, Lijian 2016-05-17 19:01:34 -07:00 committed by Aaron Durbin
parent 4001f244ad
commit 1b8ee0b88a
2 changed files with 47 additions and 0 deletions
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13
src/soc/intel/apollolake/chip.c
View File

@ -117,6 +117,19 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin; silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin;
silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin; silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin;
if (cfg->emmc_tx_cmd_cntl != 0)
silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl;
if (cfg->emmc_tx_data_cntl1 != 0)
silconfig->EmmcTxDataCntl1 = cfg->emmc_tx_data_cntl1;
if (cfg->emmc_tx_data_cntl2 != 0)
silconfig->EmmcTxDataCntl2 = cfg->emmc_tx_data_cntl2;
if (cfg->emmc_rx_cmd_data_cntl1 != 0)
silconfig->EmmcRxCmdDataCntl1 = cfg->emmc_rx_cmd_data_cntl1;
if (cfg->emmc_rx_strobe_cntl != 0)
silconfig->EmmcRxStrobeCntl = cfg->emmc_rx_strobe_cntl;
if (cfg->emmc_rx_cmd_data_cntl2 != 0)
silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2;
/* Our defaults may not match FSP defaults, so set them explicitly */ /* Our defaults may not match FSP defaults, so set them explicitly */
silconfig->AcpiBase = ACPI_PMIO_BASE; silconfig->AcpiBase = ACPI_PMIO_BASE;
/* First 4k in BAR0 is used for IPC, real registers start at 4k offset */ /* First 4k in BAR0 is used for IPC, real registers start at 4k offset */

34
src/soc/intel/apollolake/chip.h
View File

@ -40,6 +40,40 @@ struct soc_intel_apollolake_config {
uint8_t pcie_rp4_clkreq_pin; uint8_t pcie_rp4_clkreq_pin;
uint8_t pcie_rp5_clkreq_pin; uint8_t pcie_rp5_clkreq_pin;
/* [14:8] DDR mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR mode Number of dealy elements.Each = 125pSec.
*/
uint32_t emmc_tx_cmd_cntl;
/* [14:8] HS400 mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR104/HS200 mode Number of dealy elements.Each = 125pSec.
*/
uint32_t emmc_tx_data_cntl1;
/* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
* [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
* [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR12/Compatibility mode Number of dealy elements.Each = 125pSec.
*/
uint32_t emmc_tx_data_cntl2;
/* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
* [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
* [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR12/Compatibility mode Number of dealy elements.Each = 125pSec.
*/
uint32_t emmc_rx_cmd_data_cntl1;
/* [14:8] HS400 mode 1 Number of dealy elements.Each = 125pSec.
* [6:0] HS400 mode 2 Number of dealy elements.Each = 125pSec.
*/
uint32_t emmc_rx_strobe_cntl;
/* [13:8] Auto Tuning mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR104/HS200 Number of dealy elements.Each = 125pSec.
*/
uint32_t emmc_rx_cmd_data_cntl2;
/* Configure serial IRQ (SERIRQ) line. */ /* Configure serial IRQ (SERIRQ) line. */
enum serirq_mode serirq_mode; enum serirq_mode serirq_mode;