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soc/intel/apollolake: Switch to snake case for PmicPmcIpcCtrl 

For a unification of the naming convension, change from pascal case to
snake case style for parameter 'PmicPmcIpcCtrl'.

Change-Id: I3632d1e83108221d3487b4f175133ad347238bc5
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75853
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mario Scheithauer 2023-06-15 14:10:34 +02:00 committed by Jakub Czapiga
parent 67fa483235
commit 1bbdd0ad01
3 changed files with 6 additions and 6 deletions
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8
src/mainboard/google/octopus/variants/baseboard/devicetree.cb
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@ -275,18 +275,18 @@ chip soc/intel/apollolake
# RegOrValue (15:8): 0x2 and RegAndValue (7:0) 0xF8. # RegOrValue (15:8): 0x2 and RegAndValue (7:0) 0xF8.
# The register is defined as: D[7:3] RSVD, D[2:0] PWROKDELAY. # The register is defined as: D[7:3] RSVD, D[2:0] PWROKDELAY.
# uint8 RegOrValue, RegAndValue, PmicReadReg # uint8 RegOrValue, RegAndValue, PmicReadReg
# RegOrValue = (UINT8)((PmicPmcIpcCtrl >> 8) & 0xff); # RegOrValue = (UINT8)((pmic_pmc_ipc_ctrl >> 8) & 0xff);
# RegAndValue = (UINT8)(PmicPmcIpcCtrl & 0xff); # RegAndValue = (UINT8)(pmic_pmc_ipc_ctrl & 0xff);
# PmicReadReg &= RegAndValue; # PmicReadReg &= RegAndValue;
# PmicReadReg |= RegOrValue; # PmicReadReg |= RegOrValue;
# PmicReadReg value will be programmed into PMIC D[2:0] PWROKDELAY field # PmicReadReg value will be programmed into PMIC D[2:0] PWROKDELAY field
# and D[7:3] RSVD will not be impacted. # and D[7:3] RSVD will not be impacted.
# Configure PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay # Configure pmic_pmc_ipc_ctrl for PMC to program PMIC PCH_PWROK delay
# from 100ms to 10ms. # from 100ms to 10ms.
# PWROKDELAY[2:0]: 000=2.5ms, 001=5.0ms, 010=10ms, 011=15ms, 100=20ms, # PWROKDELAY[2:0]: 000=2.5ms, 001=5.0ms, 010=10ms, 011=15ms, 100=20ms,
# 101=50ms, 110=75ms, 111=100ms (default) # 101=50ms, 110=75ms, 111=100ms (default)
register "PmicPmcIpcCtrl" = "0x5e4302f8" register "pmic_pmc_ipc_ctrl" = "0x5e4302f8"
# FSP UPD to modify the Integrated Filter (IF) value # FSP UPD to modify the Integrated Filter (IF) value
# Set it to default value: 0x12 # Set it to default value: 0x12

2
src/soc/intel/apollolake/chip.c
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@ -602,7 +602,7 @@ static void glk_fsp_silicon_init_params_cb(
* improve boot performance, configure PmicPmcIpcCtrl for PMC to program * improve boot performance, configure PmicPmcIpcCtrl for PMC to program
* PMIC PCH_PWROK delay. * PMIC PCH_PWROK delay.
*/ */
silconfig->PmicPmcIpcCtrl = cfg->PmicPmcIpcCtrl; silconfig->PmicPmcIpcCtrl = cfg->pmic_pmc_ipc_ctrl;
/* /*
* Options to disable XHCI Link Compliance Mode. * Options to disable XHCI Link Compliance Mode.

2
src/soc/intel/apollolake/chip.h
View File

@ -178,7 +178,7 @@ struct soc_intel_apollolake_config {
* Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address * Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address
* (31:24) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0) * (31:24) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0)
*/ */
uint32_t PmicPmcIpcCtrl; uint32_t pmic_pmc_ipc_ctrl;
/* Options to disable XHCI Link Compliance Mode. Default is FALSE to not /* Options to disable XHCI Link Compliance Mode. Default is FALSE to not
* disable Compliance Mode. Set TRUE to disable Compliance Mode. * disable Compliance Mode. Set TRUE to disable Compliance Mode.