src/southbridge: Capitalize CPU, RAM and ROM

Change-Id: I01413b9f8b77ecdcb781340f04c2fe9e24810264
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15941
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>

src/southbridge/amd/agesa/hudson/lpc.c

@@ -63,7 +63,7 @@ static void lpc_init(device_t dev)
 				   interrupt and visit LPC. */
 	pci_write_config8(dev, 0x78, byte);
 
-	/* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI rom */
+	/* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI ROM */
 	/* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */
 	byte = pci_read_config8(dev, 0xBB);
 	byte |= 1 << 0 | 1 << 3;

src/southbridge/amd/cimx/sb700/bootblock.c

@@ -45,7 +45,7 @@ static void sb700_enable_rom(void)
 	dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ;
 	pci_io_write_config32(dev, 0x48, dword);
 
-	/* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
+	/* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */
 	/* Set the 4MB enable bits */
 	word = pci_io_read_config16(dev, 0x6c);
 	word = 0xFFC0;
@@ -54,6 +54,6 @@ static void sb700_enable_rom(void)
 
 static void bootblock_southbridge_init(void)
 {
-	/* Setup the rom access for 2M */
+	/* Setup the ROM access for 2M */
 	sb700_enable_rom();
 }

src/southbridge/amd/cimx/sb800/Kconfig

@@ -214,7 +214,7 @@ config SB800_IMC_FAN_CONTROL
 	depends on SB800_IMC_FWM
 	help
 	  Set up the SB800 to use the IMC based Fan controller.  This requires
-	  the IMC rom from AMD.  Configure the registers in devicetree.cb.
+	  the IMC ROM from AMD.  Configure the registers in devicetree.cb.
 
 endchoice
 

src/southbridge/amd/cimx/sb800/bootblock.c

@@ -44,7 +44,7 @@ static void enable_rom(void)
 	dword |= (1 << 0) | (1 << 1) | (1 << 4) | (1 << 6) | (1 << 21);
 	pci_io_write_config32(dev, 0x48, dword);
 
-	/* Enable rom access */
+	/* Enable ROM access */
 	word = pci_io_read_config16(dev, 0x6c);
 	word = 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6);
 	pci_io_write_config16(dev, 0x6c, word);
@@ -107,7 +107,7 @@ static void enable_clocks(void)
 
 static void bootblock_southbridge_init(void)
 {
-	/* Setup the rom access for 2M */
+	/* Setup the ROM access for 2M */
 	enable_rom();
 	enable_prefetch();
 	enable_spi_fast_mode();

src/southbridge/amd/cimx/sb900/bootblock.c

@@ -44,7 +44,7 @@ static void sb900_enable_rom(void)
   dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ;
   pci_io_write_config32(dev, 0x48, dword);
 
-  /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
+  /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */
   /* Set the 4MB enable bits */
   word = pci_io_read_config16(dev, 0x6c);
   word = 0xFFC0;
@@ -53,6 +53,6 @@ static void sb900_enable_rom(void)
 
 static void bootblock_southbridge_init(void)
 {
-  /* Setup the rom access for 2M */
+  /* Setup the ROM access for 2M */
   sb900_enable_rom();
 }

src/southbridge/amd/cs5535/chipsetinit.c

@@ -310,7 +310,7 @@ chipsetinit(void)
 	outl	(GPIOL_2_SET, GPIOL_IN_AUX1_SELECT);
 
 	/*  Allow IO read and writes during a ATA DMA operation. */
-	/*   This could be done in the HD rom but do it here for easier debugging. */
+	/*   This could be done in the HD ROM but do it here for easier debugging. */
 
 	msrnum = ATA_SB_GLD_MSR_ERR;
 	msr = rdmsr(msrnum);

src/southbridge/amd/cs5536/cs5536.c

@@ -560,7 +560,7 @@ void chipsetinit(void)
 	outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
 
 	/*      Allow IO read and writes during a ATA DMA operation. */
-	/*       This could be done in the HD rom but do it here for easier debugging. */
+	/*       This could be done in the HD ROM but do it here for easier debugging. */
 	msrnum = ATA_SB_GLD_MSR_ERR;
 	msr = rdmsr(msrnum);
 	msr.lo &= ~0x100;

src/southbridge/amd/pi/hudson/lpc.c

@@ -63,7 +63,7 @@ static void lpc_init(device_t dev)
 				   interrupt and visit LPC. */
 	pci_write_config8(dev, 0x78, byte);
 
-	/* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI rom */
+	/* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI ROM */
 	/* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */
 	byte = pci_read_config8(dev, 0xBB);
 	byte |= 1 << 0 | 1 << 3;

src/southbridge/amd/rs690/early_setup.c

@@ -279,7 +279,7 @@ static void rs690_por_pcicfg_init(device_t nb_dev)
 	/* Power Management Register Enable */
 	set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x80);
 
-	/* Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge
+	/* Reg4Ch[1]=1 (APIC_ENABLE) force CPU request with address 0xFECx_xxxx to south-bridge
 	 * Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation
 	 * BMMsgEn */
 	set_nbcfg_enable_bits_8(nb_dev, 0x4C, (u8)(~0x00), 0x42 | 1);

src/southbridge/amd/rs690/rs690.c

@@ -116,7 +116,7 @@ static u32 get_vid_did(device_t dev)
 *	0:06.0  P2P	: bit 6 of nbmiscind 0x0c : 0 - enable, default	   + 32 * 2
 *	0:07.0  P2P	: bit 7 of nbmiscind 0x0c : 0 - enable, default	   + 32 * 2
 *	0:08.0  NB2SB	: bit 6 of nbmiscind 0x00 : 0 - disable, default   + 32 * 1
-* case 0 will be called twice, one is by cpu in hypertransport.c line458,
+* case 0 will be called twice, one is by CPU in hypertransport.c line458,
 * the other is by rs690.
 ***********************************************/
 void rs690_enable(device_t dev)

src/southbridge/amd/rs780/early_setup.c

@@ -419,7 +419,7 @@ static void rs780_por_pcicfg_init(device_t nb_dev)
 	/* Power Management Register Enable */
 	set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x80);
 
-	/* Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge
+	/* Reg4Ch[1]=1 (APIC_ENABLE) force CPU request with address 0xFECx_xxxx to south-bridge
 	 * Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation
 	 * BMMsgEn */
 	set_nbcfg_enable_bits_8(nb_dev, 0x4C, (u8)(~0x00), 0x42 | 1);

src/southbridge/amd/rs780/rs780.c

@@ -262,7 +262,7 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
 *	0:06.0  P2P	: bit 6 of nbmiscind 0x0c : 0 - enable, default	   + 32 * 2
 *	0:07.0  P2P	: bit 7 of nbmiscind 0x0c : 0 - enable, default	   + 32 * 2
 *	0:08.0  NB2SB	: bit 6 of nbmiscind 0x00 : 0 - disable, default   + 32 * 1
-* case 0 will be called twice, one is by cpu in hypertransport.c line458,
+* case 0 will be called twice, one is by CPU in hypertransport.c line458,
 * the other is by rs780.
 ***********************************************/
 void rs780_enable(device_t dev)

src/southbridge/amd/sb800/lpc.c

@@ -59,7 +59,7 @@ static void lpc_init(device_t dev)
 				   interrupt and visit LPC. */
 	pci_write_config8(dev, 0x78, byte);
 
-	/* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI rom */
+	/* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI ROM */
 	/* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */
 	byte = pci_read_config8(dev, 0xBB);
 	byte |= 1 << 0 | 1 << 3;

src/southbridge/amd/sb800/sm.c

@@ -83,7 +83,7 @@ static void sm_init(device_t dev)
 	printk(BIOS_INFO, "sm_init().\n");
 
 	/* Don't rename APIC ID */
-	/* TODO: We should call setup_ioapic() here. But kernel hangs if cpu is K8.
+	/* TODO: We should call setup_ioapic() here. But kernel hangs if CPU is K8.
 	 * We need to check out why and change back. */
 	clear_ioapic(VIO_APIC_VADDR);
 	//setup_ioapic(IO_APIC_ADDR, 0);

src/southbridge/amd/sr5650/early_setup.c

@@ -343,7 +343,7 @@ static void sr5650_por_pcicfg_init(device_t nb_dev)
 	set_nbcfg_enable_bits(nb_dev, 0x20, ~0, 0x0);
 	set_nbcfg_enable_bits(nb_dev, 0x84, ~0, 0x03000010);
 
-	/* Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge
+	/* Reg4Ch[1]=1 (APIC_ENABLE) force CPU request with address 0xFECx_xxxx to south-bridge
 	 * Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation
 	 * BMMsgEn */
 	set_nbcfg_enable_bits(nb_dev, 0x4C, (u8)(~0x00), 0x52042);

src/southbridge/amd/sr5650/sr5650.c

@@ -564,7 +564,7 @@ void sr5650_nb_pci_table(device_t nb_dev)
 	printk(BIOS_DEBUG, "NB_PCI_REG04 = %x.\n", temp16);
 	temp32 = pci_read_config32(nb_dev, 0x84);
 	printk(BIOS_DEBUG, "NB_PCI_REG84 = %x.\n", temp32);
-	//Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge
+	//Reg4Ch[1]=1 (APIC_ENABLE) force CPU request with address 0xFECx_xxxx to south-bridge
 	//Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation
 	pci_write_config8(nb_dev, 0x4c, 0x42);
 	temp8 = pci_read_config8(nb_dev, 0x4e);
@@ -605,7 +605,7 @@ void sr5650_nb_pci_table(device_t nb_dev)
 *	0:06.0  P2P	: bit 6 of nbmiscind 0x0c : 0 - enable, default	   + 32 * 2
 *	0:07.0  P2P	: bit 7 of nbmiscind 0x0c : 0 - enable, default	   + 32 * 2
 *	0:08.0  NB2SB	: bit 6 of nbmiscind 0x00 : 0 - disable, default   + 32 * 1
-* case 0 will be called twice, one is by cpu in hypertransport.c line458,
+* case 0 will be called twice, one is by CPU in hypertransport.c line458,
 * the other is by sr5650.
 ***********************************************/
 void sr5650_enable(device_t dev)

src/southbridge/intel/bd82x6x/early_me.c

@@ -156,7 +156,7 @@ int intel_early_me_init_done(u8 status)
 	printk(BIOS_NOTICE, "ME:  Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24);
 	printk(BIOS_NOTICE, "ME:  Progress code   : 0x%x\n", (me_fws2 & 0xf0000000) >> 28);
 
-	// Poll cpu replaced for 50ms
+	// Poll CPU replaced for 50ms
 	millisec = 0;
 	while ((((me_fws2 & 0x100) >> 8) == 0) && millisec < 50) {
 		udelay(1000);

src/southbridge/intel/i82371eb/fadt.c

@@ -78,11 +78,11 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 	fadt->cst_cnt = 0; /* smi command to indicate c state changed notification */
 	fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */
 	fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */
-	fadt->flush_size = 0; /* only needed if cpu wbinvd is broken */
+	fadt->flush_size = 0; /* only needed if CPU wbinvd is broken */
 	fadt->flush_stride = 0;
 	fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */
 	fadt->duty_width = 3; /* this width is in bits */
-	fadt->day_alrm = 0x0d; /* rtc cmos ram offset */
+	fadt->day_alrm = 0x0d; /* rtc cmos RAM offset */
 	fadt->mon_alrm = 0x0; /* not supported */
 	fadt->century = 0x0; /* not supported */
 	/*