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Documentation/releases: Improve CSME section 

1.  Fix typo in *based*
2.  Use official spelling for Alder Lake
3.  Mention *Converged Security*
4.  Capitalize CMOS

Change-Id: I36eac6f017229a3e9261e0eb84371421927e1cae
Fixes: 941239d54d (Documentation/releases: Update 4.16 release notes)
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Paul Menzel 2021-12-15 10:12:37 +01:00 committed by Felix Held
parent 7f5a1eeb24
commit 1ca8b6e3c3
1 changed files with 6 additions and 5 deletions
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11
Documentation/releases/coreboot-4.16-relnotes.md
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@ -19,8 +19,9 @@ Significant changes
### Add significant changes here ### Add significant changes here
### Option to disable Intel Management Engine ### Option to disable Intel Management Engine
Disable the Intel (CS)Management Engine via HECI based on Intel Core processors Disable the Intel (Converged Security) Management Engine ((CS)ME) via HECI based
from Skylake to Alderlake. State is set baed on a cmos value of `me_state`. A on Intel Core processors from Skylake to Alder Lake. State is set based on a
value of `0` will result in a (CS)ME state of `0` (working) and value of `1` CMOS value of `me_state`. A value of `0` will result in a (CS)ME state of `0`
will result in a (CS)ME state of `3` (disabled). For an example cmos layout and (working) and value of `1` will result in a (CS)ME state of `3` (disabled). For
more info, see [cse.c](../../src/soc/intel/common/block/cse/cse.c). an example CMOS layout and more info, see
[cse.c](../../src/soc/intel/common/block/cse/cse.c).